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Video Series 22: Supporting multiple video resolutions on ZC702 HDMI

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Welcome to the Xilinx Design and Debug Techniques blog, a new weekly blog where our Applications Engineers share their experiences and lessons learned designing and debugging with Xilinx.

This first entry is a continuation of the Video Series from the Video board.

The Video Series will be published here from now on, along with entries from other Xilinx Engineers on their areas of expertise.

You can see all previous entries in the Video series here.



In the previous Video Series entry (Number 21), we created a design which sends a pattern (using the LogiCORE™ IP Video Test Pattern Generator (TPG) core) to the on-board HDMI of a Zynq®-7000 SoC ZC702 Evaluation Kit.

However, for this application, the resolution was fixed to 800x600p in the hardware design (there was no option to change it in the application).

In this Video Series we will see how to modify the hardware design and the application to support multiple video resolutions.



Tutorial – Supporting multiple HDMI resolutions (TX) on a ZC702 evaluation board


Note: This tutorial is intended to be used only with Vivado Design Suite 2018.1, and only with a ZC702 evaluation board.

Build the Vivado project

1) Download the tutorial files and unzip the folder.

2) Open Vivado Design Suite 2018.1.

3) In the Tcl console, cd into the unzipped directory:

cd <path>/XVES_0022

4) In the Tcl console, source the script Tcl:

source ./create_proj.tcl

Note: A valid license for the Test Pattern Generator is required to build the design.

Add configuration interfaces (AXI4-Lite)

5) Double-click on the Video Timing Controller (VTC) IP to open its configuration GUI.

6) Enable Include AXI4-Lite Interface. This will allow us to configure the VTC IP from the processor, and so from the software application.




 7) Click on the Default/Constant tab and expand the Video Mode option. You can see all of the preset resolutions included in the VTC IP.




In this video series, we will only support 800x600p, 1024x768p and 720p (1280x720p).

Looking on the web we can find the pixel clock for these resolutions, 65Mhz for 1024x768p and 74.25MHz for 1280x720p.

(Note that the clock required for 800x600 is 40Mhz).

Keep the video mode as 800x600p.

9) Close the VTC IP configuration GUI by clicking on OK.

10) On the Block Design click on Run Connection Automation.



11) Make sure All Automation is selected and click OK.




Vivado will automatically connect the VTC IP to the Zynq processor.





12) Double-click on the Clocking Wizard (clk_wiz_0) to open its configuration GUI.

13) Click on the Clocking Option tab and enable Dynamic Reconfig.





14) In the Output Clocks tab, make sure that clk_out1 is set to 40MHz, then enable clk_out2 and clk_out3 and set their frequency to 65MHz and 74.25MHz.





15) Go to the MMCM Settings tab and check the MMCM configuration Divide value for the 3 clocks.


16) Click on Allow Override Mode to keep the MMCM settings.


17) Go back to the the Output Clocks tab and disable clk_out2 and clk_out3.

We will use only clk_out1, changing its Divide setting to change its frequency.

18) Click OK to close the Clocking Wizard configuration GUI.

19) On the Block Design, click on Run Connection Automation, make sure that the All Automation option is enabled, and click OK.



20) Validate the Block Design (BD). You should have no error or critical warnings. Save the BD.

21) In the sources window, right click on the BD and select Generate Output Products.

22) When the Output Product Generation is completed, right click on the BD and select Create HDL Wrapper.

23) Run Vivado Synthesis and Vivado Implementation, and Generate the Bitstream.


Create the Software Development Kit (SDK) Application

24) Export the Hardware to SDK. Click File > Export > Export Hardware.


25) Make sure that Include Bitstream is enabled and change the export location to <path>/XVES_0022/sdk_export.



26) Close Vivado.

27) Start the Xilinx Software Command Line Tool (XSCT) 2018.1.

  • From the Windows menu:
    Start > All Programs > Xilinx Design Tools > Xilinx Software Command Line Tool 2018.1.


  • From the command line
    Use the command xsct (the environment variables for SDK 2018.1 need to be set)

28) In xsct, cd to the path of the extracted folder. Then enter the command below:

source create_SW_proj.tcl


29) Open SDK and select XVES_0022/sdk_workspace.

This application is based on the application from the previous Video Series. Note that in this version, the VTC Generator is enabled in the code when the application is starting.

Test the application

30) Build the tpg_hdmi_zc702_app application.

31) Make sure you have the ZC702 connected to the UART, the JTAG, and the HDMI.

32) Click on Xilinx > Program FPGA. Then select program.

33) In SDK, in the project explorer, right click on the tpg_hdmi_zc702_app application and select Run As > Launch on Hardware (System Debugger).

Note: This step assumes that your board is connected locally and not through a server.



You should see a pattern displayed on the monitor with a green moving box.

If you go the monitor menu, you will see that it is correctly displaying a 800x600@60Hz image.



Update the application to use another output resolution

You will first need to change the configuration of the clocking wizard. The only parameter you need to change in the clocking wizard is the CLKOUT0 DIV in register 0x208.

Note that the bits [17:8] of the register represent the fractional part of the DIV value and the bits [7:0] the integer part.

To set the DIV to 16 (for our 65MHz) the register value will be 0x10.  To set the DIV to 26 (for our 40MHz) the register value will be 0x1A.

34) Add the following code to the application (tpg_hdmi_ZC702.c):

/* Clocking Wizard Configuration */
//Configure the CLKOUT0 DIV
Xil_Out32(ClkWiz_CfgPtr->BaseAddr + 0x208, 0x0010);

/* End of clocking wizard configuration */

  You will then need to load the clock configuration by setting the value 0x1 in the register 0x25C of the Clocking Wizard.

35) Add the following code to the application:

/* Clocking Wizard Configuration */

//Configure the CLKOUT0 DIV
Xil_Out32(ClkWiz_CfgPtr->BaseAddr + 0x208, 0x000A);
Xil_Out32(ClkWiz_CfgPtr->BaseAddr + 0x25C, 0x3);

/* End of clocking wizard configuration */

36) Change the TPG output resolution in the application to 1024x768.

//Configure the TPG
app_hdmi_conf_tpg(&tpg_inst, 768, 1024, 0x2, XTPG_BKGND_COLOR_BARS);

 Finally, you will need to change the configuration of the VTC.

37) Add the following code to the application.

Note that VMODE_XGA represent the 1024x768 video resolution (use XVTC_VMODE_SVGA for 800x600 and XVTC_VMODE_720P for 720P)

/* VTC Configuration */
XVtc_SetGeneratorTiming(&VtcInst, &XVtc_Timingconf);

/* End of VTC Configuration */

  38) Re-build the application, re-program the PL (Xilinx > Program FPGA) and re-launch the application.

The monitor menu should now indicate that the output resolution is 1024x768 as expected.



39) Try to change the application to display a 720p output.

Note that the method presented in this tutorial (using the clocking wizard) is only one way of changing the video clock. The ZC702 kit has a programmable clock which can also be used for this purpose.


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Is there a typo here on this line: " To set the DIV to 10 (for our 65MHz) the register value will be 0x08".

It should be " will be 0x10". -  250 is 0xFA, 16 is 0x10 for DIV to 16.250


Hi @dimiter 

You are right, there were two typos in these lines. I have corrected them:

Note that the bits [17:8] of the register represent the fractional part of the DIV value and the bits [7:8] [7:0] the integer part.

To set the DIV to 10 (for our 65MHz) the register value will be 0x08 0x0A.  To set the DIV to 16.250 (for our 40MHz) the register value will be 0xFA10.

Thank you for your review.

Best Regards


Hello @florentw ...

I am using ZedBoard and I followed the lessonns from 19 through 21, unfortunately the HDMI didn't work  with me, so I tried multiple things.


Ps I2C wiht default MIO didn't work, so I changed it to EMIO and map it manually in the constraints file and it worked.


After that HDMI didn't work with the "sys_diff_clock" (sure after I modified the constraints file), so I tried to feed the clk wizard with 100MHz clk from zynq processing system and it worked, but this lesson didn't work with me (I made sure I2C is working) and I am wondering why project didn't work with "sys_diff_clock" and if it would work if I change the clock in this lesson?

Thank you...


Hi @Abady 

I do not believe the PL clock Zedboard is a differential clock. There is one PL clock on the zedboard which is connected to pin Y9. And the frequency for this clock is 100MHz (compared to the ZC702 differential clock which is 200MHz).

You need to take this in account. Please make sure you review the User Guide of both board to understand the differences.

If you have further question on this, please create a topic on the Audio and Video Board of the forums.




You say that 720p has a clock of 72.2 MHz. Where did you get this value from? Shouldn't it be 74.25 MHz?


Hi @beandigital 

You are correct. Checking on CEA-861-D spec this is 74.25 MHz. Not sure why I did it with 72.2MHz at the time. Thanks you for the correcting me