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Video Series 24: Using the AXI VDMA in Triple Buffer Mode

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In this Video Series we will see how we can integrate the AXI VDMA IP configured in Triple Buffer Mode into a Video Pipeline in a Vivado design.



The design will be made for a Zynq®-7000 SoC ZC702 Evaluation Kit using the PS DDR. However, the same steps could be applied to other Zynq based video designs such as the example from the previous video series on the PYNQ™ board.


Tutorial – Adding a VDMA in Triple Buffer mode to a Video Design

Note: This tutorial and the attached files are intended to be used only with Vivado Design Suite 2018.1, and only with a ZC702 evaluation board.

Build the Vivado project

  1. Download the tutorial files and unzip the folder.

  2. Open Vivado 2018.1.

  3. In the Tcl console, cd into the unzipped directory (cd <path>/XVES_0024).

  4. In the Tcl console, source the script tcl (source ./create_proj.tcl).

Note: A valid license for the Test Pattern Generator is required to build the design.

Add an AXI VDMA to the Video Pipeline

  1. Disconnect the AXI4-Stream interface between the AXI4-Stream Subset Converter and the AXI4-Stream to Video Out.



  1. Add an AXI Video Direct Memory Access (VDMA) to the Block Design (BD).

  2. Connect the S_AXIS_S2MM input of the AXI VDMA to the M_AXIS output of the AXI4-Stream Subset Converter and connect the M_AXIS_MM2S output of the VDMA to the video_in output of the AXI4-Stream to Video Out.



Connect the AXI VDMA to the memory (PS DDR)

To connect the AXI VDMA to the PS DDR we need to go through the Zynq Processor and enable an AXI Memory Mapped input on the Zynq processing system.

  1. Double click on the ZYNQ7 Processing System to open its configuration GUI.
  2. In the PS-PL Configuration Section, enable the S AXI HP0 interface under HP Slave AXI Interface. Click OK to close the Zynq configuration GUI.



  1. Connect the S_AXI_HP0_ACK input to the FCLK_CLK0 output from the ZYNQ processing system.



  1. Click on Run Connection Automation to let Vivado automatically connect the interfaces of the AXI VDMA.

  1. In the Run Connection Automation window, make sure All Automation is selected and click OK.

  2. Vivado might suggest the Run Connection Automation option again for the M_AXI_S2MM interface. If this is the case, click on Run Connection Automation again, make sure All Automation is selected, and click OK.

Note: In this example, we are only using one clock and one memory for the full design.

As a result, in the Run Connection Automation option, we do not have many options. With a more complex design, you might need to be careful when using this feature.

Configure the VDMA

  1. Validate the BD. You will receive the following warning:
    CRITICAL WARNING: [BD 41-237] Bus Interface property TDATA_NUM_BYTES does not match between /v_axi4s_vid_out_0/video_in(2) and /axi_vdma_0/M_AXIS_MM2S(4)

This is because we are missing one configuration in the AXI VDMA: the width of the AXI4-Stream interface to match the design.

  1. Double click on the AXI VDMA to open its configuration GUI. Change the Stream Data Width parameter for the Read Channel to 16. Click OK to close the AXI VDMA configuration GUI (keep all of the other parameters at their default values).



Note: By default, the AXI VDMA is configured with 3 frame buffers (this is why we called it Triple Buffer Mode, which is the most common use case for this IP)

  1. Re-validate the BD. You should have no warnings or errors. Save the BD.

Generate the design

  1. Right click on the BD in the sources window and click Generate Output Products.

  2. When the output product generation is over, right click on the BD in the sources window and click Generate HDL wrapper.

  3. Run Synthesis and Implementation, and Generate the Bitstream.

  4. Export the Hardware to SDK. Click File > Export > Export Hardware.



  1. Make sure Include Bitstream is enabled and change the export location to <path>/XVES_0024/sdk_export.

  2. Close Vivado.

Create the Software Application

  1. Start the Xilinx Software Command Line Tools (XSCT) 2018.1.
  • From Windows:

Start > All Programs > Xilinx Design Tools > Xilinx Software Command Line Tool 2018.1.

  • From the command line

Use the command xsct (the environment variables for SDK 2018.1 needs to be set).

  1. In xsct, cd to the path of the extracted folder. Then enter the command source create_SW_proj.tcl.


  1. Open SDK and select XVES_0024/sdk_workspace as the workspace.

Manage the memory

One thing to be careful of when using memory for data is to make sure that the processor is not using the same part of the memory.

  1. Double click on the linker script ld under the vdma_zc702_app to open it.



In the Section to Memory Region Mapping table in the linker script, we can see that the processor will be using the PS DDR. We can restrict the amount of memory available to the processor to make sure there is no overlap.

  1. In the Available Memory Region, change the size of the ps7_ddr_0 to 0xEFFFFF and save the linker script.


In the design, the PS memory (1G) is mapped from 0x0 to 0x3FFF_FFFF. This means that we can use the memory from 0x100_0000 to 0x3FFF_FFFF for the video data from the VDMA without having the processor code at the same location.


Configure and Start the AXI VDMA

To configure the VDMA we can follow the General Use Case from page 72 of (PG020) starting with the write channel:



  1. Configure S2MM_VDMACR (30h) to 8Bh using the following code:
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x8B);

For the frame size address, we need to know how much memory we will need for a frame. The width of the AXI4-Stream going to/from the VDMA is 2 bytes and our image size is 800x600. The amount of memory we need for one frame is as follows:

2 * 800 * 600 = 960,000 bytes (0xEA600).

If our first frame buffer is placed at the address 0x1000_0000, we will need to place the second frame buffer at 0x100E_A600 or higher.

We can try to keep some margin and place the frame buffers every 0xF0000. This give us the following addresses:

Frame buffer 1 -> 0x1000_0000

Frame buffer 2 -> 0x100F_0000

Frame buffer 3 -> 0x101E_0000

  1. Configure the start address for the three frame buffers with the following code:
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, 0x10000000);
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB0, 0x100F0000);
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB4, 0x101E0000);

Then we need to configure the STRIDE and the HSIZE. I will explain the use of the HSTRIDE in a future use case.

For most cases, it can have the same value as HSIZE. This is what we will use in this application. Note that HSIZE and STRIDE need to be entered in bytes. As we have a 2-byte wide stream interface, we need to multiply the horizontal size by 2.

  1. Configure the STRIDE and HSIZE with the following code:
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, 800*2);
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 800*2);
  1. Finally, add the following code to set the VSIZE:
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, 600);

The read channel configuration then follows the same steps. We can configure it with the same parameters:



  1. Add the following code to configure the read channel:
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x8B);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, 0x10000000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, 0x100F0000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, 0x101E0000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, 800*2);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, 800*2);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, 600);

Test the application

  1. Build the application (Project > Build All).

  2. Program the FPGA (Xilinx > Program FPGA) and launch the application (right click on the application > Run As > Launch on Hardware (System Debugger)).

You should see a color bar pattern correctly displayed on the monitor which means that the video is correctly going through the VDMA.


Want more from this Video Series?




Is there any plans to make an example for hdmi-out + zc702 + linux with current version of Vivado and kernel ?



Hi @zbyszekt ,

I do not have any plan in the coming months.




Dear @florentw ,

Thanks for this useful post. I am able to run your codes. It works successfully. I can see color bar in monitor.

But, I want to change resolution. How can I change resolution of the video? I basicly changed height & width of video in the below line in SDK. I also changed resolution settings in VDMA configurations. SW can come to while(1) loop without any problem. But video is not seen on the screen. Is there any suggestion?

Thank you so much, 

app_hdmi_conf_tpg(&tpg_inst, 1080, 1920, 0x2, XTPG_BKGND_COLOR_BARS);



Hi @doner_t ,

The output resolution is fixed because the video clock inside the vivado design is fixed. You would need to reconfigure the MMCM (through the clocking wizard) either fixed in vivado or through the processor (you first need to enable the AXI4-Light interface for the clocking wizard).

This is explained in my video series 22  (for a full understanding of the system you might want to start my video series from the beginning. See the main page for the video series)



I have no access to ZC702 board so I did this with Zybo board and VGA output. My block Design is found below. At the level of the initialization of the VDMA, I get xst_failure. What could be the problem? My stream frequency  is 150Mhz and clock frequency is 40Mhz(800x600). The screenshot of the VDMA configuration is also found below.Capture.PNGCapture1.PNG


Hi @baring42read 

Please create a new topic on the Video Board for this question


So thank you very much ,this is very useful. thanks again!