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Video Series 31 – Debugging a Video System using an ILA

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Introduction

The most important part in debugging a video system is to understand what part of the video system is failing. This helps to determine where to focus the debugging.

A good way to look for the failure inside the FPGA is to look at the inputs/outputs of the different IP cores in the design. For this we can use an Integrated Logic Analyzer (ILA).

The Xilinx ILA is documented in the (PG172) and tutorials are provided in (UG936) Vivado Design Suite Tutorial - Programming and Debugging.

In this Video Series entry we will cover 2 different methods for ILA insertion (netlist insertion and instantiation in IP Integrator) and how we can use the ILA to debug a video system.

 

When debugging a Video system, I would recommend the following placement for the ILA:

  • If this is a new video project, add the ILA at the source (beginning) or at the sink (end) of the video pipeline. I usually start at the source.
  • If you had a previously working video design and you have only added one IP, I would start by looking at the input and output of this IP.

 

The main thing you want to look at is the AXI4-Stream interface of the IP and more specifically the following signals:

  • tvalid: if the signal tvalid stays low, this means that the up-stream (source) IP is not sending data, so you might want to investigate this IP.

Note that it can be the source of the source of the source etc… which has an issue. So you might need to have another ILA on an upstream IP (unless you are at the start of the video pipeline)

  • tready: if the signal tready stays low, this means that the down-stream (sink) IP is not able to receive more data, so you might want to investigate this IP

Note that it can be the sink of the sink of the sink etc… which has an issue

  • tdata, tuser, and tlast: You might want to look at these signals if tready and tvalid seem to be behaving correctly or if you have an output, but the content on the monitor is not great

 

For the two following labs you will need to use the design files attached to this Video Series entry.

 


 

Lab 1 - Using the Netlist Insertion Method – Adding Mark debug on the synthesis results

Note: This tutorial is intended to be used only with Vivado 2019.1 and only with a Zynq®-7000 SoC ZC702 Evaluation Kit

Generate the Design

  1. Open Vivado 2019.1.

  2. In the Tcl console, cd into the unzipped directory (cd XVES_0031/lab1).

  3. In the Tcl console, source the script tcl (source ./create_proj.tcl).

  4. Generate the BD output products then run Synthesis.

Add the ILA to the Netlist

  1. In the Flow Navigator under the Synthesis drop-down list, click Open Synthesized Design:

1.jpg

 

  1. In the netlist window, select the TPG IP and the VPSS IP (using Ctrl + click) under ZC702_ILA_DEBUG_wrapper > ZC702_ILA_DEBUG_i:

2.jpg

 

  1. Press F4 to show the schematic. It shows the connection between the 2 IP cores:

3.jpg

 

  1. Right-click on the net connecting the tlast signals of both IP cores and click Mark Debug:

4.jpg

 

  1. Repeat the same operation for the signals tuser, tready, tdata, and tvalid.

  2. Use Ctrl + S to save the design.

  3. Click OK on the next window:

5.jpg

 

  1. On the next window, keep the default settings (save constraint to ZC702.xdc) and click OK:

6.jpg

 

  1. If you check the constraints file ZC702.xdc you can see that Vivado has added lines with "set_property MARK_DEBUG":

7.jpg

  1. In the Window drop-down menu, select Debug. When the Debug window opens, click the window if it is not already selected.

  2. In the debug window, click on the bug icon (set up debug):


8.jpg

 

  1. When the Set up Debug wizard opens, click Next

  2. In the Nets to Debug window, you should see 28 Nets to debug. Click Next:

9.jpg

 

  1. Click Next and Finish in the following two windows.

  2. You can see in the design schematic that an ILA was added to the design:

10.jpg

 

  1. Use Ctrl + S to save the design.

  2. Run Implementation and generate the bitstream.

Do not close Vivado. You can now follow lab 3 to see how we can use the ILA with this design.

 


 

Lab 2 - Using the IP Instantiation Method

Note: This tutorial is intended to be used only with Vivado 2019.1 and only with the The Zynq-7000 SoC ZC702 Evaluation Kit

While the method presented in Lab 1 allows the user to connect the ILA to a net inside the IP, I recommend the method used in this Lab 2 as it really is easier and quicker.

Generate the Design

  1. Open Vivado 2019.1.

  2. In the Tcl console, cd into the unzipped directory (cd XVES_0031/lab2).

  3. In the Tcl console, source the script tcl (source ./create_proj.tcl).

Add the ILA to the Block Design (BD)

  1. Right-click on the DB and click Add IP.

  2. Add the System ILA IP.

  3. Double click on the System ILA IP to open its configuration GUI.

  4. In the Interface Options tab, change the Interface type to com:interface:axis rtl:1.0 and click OK. This sets the ILA input to AXI4-Stream:

11.jpg

 

  1. Connect the ILA Input SLOT_0_AXIS to the TPG output:

12.jpg

 

  1. Click Run Connection Automation to let the tool connect the clock and reset signal.

  2. Validate the BD. You should get no errors or critical warnings.

  3. The ILA is added. now you just need to generate the BD output products, run synthesis and implantation, and generate the bitstream.

Do not close Vivado. You can now follow lab 3 to see how we can use the ILA with this design.

 


 

Lab 3 - Using the Netlist Insertion Method – Adding Mark Debug on the synthesis results

 

Note: This tutorial is intended to be used only with Vivado 2019.1 and only with the Zynq-7000 SoC ZC702 Evaluation Kit

 

  1. In Vivado, export the HDF generated from lab1 or lab2 to XVES_0031/lab3/sw/sdk_export

  2. Start the Xilinx Software Command Line Tool (XSCT) 2019.1
  • From the Windows menu:

Start > All Programs > Xilinx Design Tools > Xilinx Software Command Line Tool 2019.1

  • From the command line:

Use the command xsct (the environment variables for SDK 2019.1 need to be set)

  1. In xsct, cd to XVES_0031/lab3.

  2. Use the following command:

    source create_SW_proj.tcl

  3. Open SDK and select XVES_0031/lab3/sdk_workspace as the workspace.

  4. Switch back to Vivado and program the PL of the ZC702 board.
    1. Open Hardware Manager > Open Target > Auto Connect
    2. Program Device > xc7v020_1
    3. Program

Note that in the Program Device window, we are loading 2 files:

  • The bitstream file (.bit) to program the FPGA
  • The Debug Probes File (.ltx) which will give the information to Vivado about what signals are captured in the ILA

13.jpg

You will get the following error message:

WARNING: [Labtools 27-3361] The debug hub core was not detected.

Resolution:
Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.

For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).

WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.

 

This message does not appear because the ILA was not programed in the PL, but because it is not detected by Vivado.

The reason for this is that we are on Zynq and the ILA is clocked by a clock coming from the Zynq processor.

As the Zynq processor is not initialized, the clock is not running and so the ILA is not detected.

To initialize Zynq, we just have to run the application in SDK (which will call ps7_init to configure the Zynq processor).

  1. Switch back to SDK.

  2. Build the application (Project > Build All), program the FPGA (Xilinx > Program FPGA) and launch the application in Debug mode (right click on the application and select Debug As > Launch on Hardware (System Debugger)).

The Debug should stop at the main entry, but this is enough to get the Zynq processor configured.

  1. In Vivado, click on refresh device. Vivado should now be able to see the ILA.

  2. In the ILA window, click on the run immediate trigger button:
    14.jpg

    We can now see the current state of the interface:

 

15.jpg

 

We can see that no transaction is happening and that tready is high but not tvalid. This is because we need to start the TPG from the application.

Before starting the TPG, we will add a trigger to try to capture the first frame.

 

  1. In the Trigger setup window, add a new trigger on the TUSER signal when TUSER equals 1:

 

16.jpg

 

  1. In the waveform window, click on the run trigger button:

 

17.jpg

 

  1. In SDK, click Resume (or press F8) to run the full application:

 

18.jpg

 

Note: Make sure that you have a HDMI monitor connected to the ZC702 board.

You should see the pattern generated on the HDMI monitor

 

  1. In the waveform window in Vivado you can see the first transaction happening, with a rising edge on TUSER indicating the start of frame:

 

19.jpg

 

Note that the tready is going low. This is probably because the VPSS was not fully ready to accept data on the first frame. If you re-run the trigger, you should see more transactions happening.

 


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