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Video Series 32 - Visualizing the Video_Mixer example design using the ZC702 evaulation kit's On-Board HDMI (Part 1 - Vivado Project)

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This video Series entry shows an example of the Hardware Design which can use the On-Board HDMI output of the Zynq®-7000 SoC ZC702 evaluation kit using the ADV7511 to visualize the Video Mixer example design.

The Video Mixer example design is originally described in Chapter 5 of (PG243).

Video Series XX_1.png

  • The design will need a software application to work. This will be done in the following Video Series entry (Number 33). This series also has a prerequisite of Video Series 19 and, Video Series 20, which describe the ADV7511.




  1. Video Mixer Overview
  2. Tutorial - Integration of the Video Mixer Example design and On-Board HDMI on the ZC702 board (Hardware Only)
  3. Next Steps 


Video Mixer Overview

The Video Mixer is used to combine up to 17 video layers and an optional logo layer to create a single video output.

For more information, see the product webpage and the IP Product Guide PG243

Video Series XX_2.png


Tutorial - Integration of the Video Mixer Example design and On-Board HDMI on the ZC702 board (Hardware Only)


The example designs for the Video Mixer described in Chapter 5 of (PG243) are targeted at the KC705, ZCU102, ZCU104 or ZCU106.

These are useful designs, but it does not allow the user to visualize the design. For video applications, being able to see the result displayed on a monitor is extremely helpful.

To allow this, this Video Series 32 will demonstrate how to implement the example design on the ZC702 board and use the ZC702's onboard ADV7511.

The design is built by replicating the Vivado example design for the ZCU104.

For any migration of an example design, Xilinx recommends building the reference design for a supported board as a reference and then replicating the design by adding the IPs individually.

Changing the target board/device for the Vivado project is not recommended as it could break the design.

Note: This tutorial is intended to be used only with Vivado 2019.1 and only with the ZC702 board.


Build The Vivado Project

  1. Download the files included with this Tutorial.
  2. Open Vivado 2019.1.
  3. In the Tcl console, navigate to the unzipped directory. (cd XVES_0032/hw)
  4. In the Tcl console, source the script tcl (source ./create_proj.tcl)


    The block design already has an AXI4-Stream to Video Out IP configured for YUV422 and connected to the Block Design (BD) output, VTC, TPG, and an AXI4-Stream Subset Converter. The setup of these IP cores is described in video series entry 19.

    The project includes a constraints file (ZC702.xdc) containing the pin locations for the design outputs. These constraints are taken from Appendix C of (UG850) (with the pin names changed to match the BD outputs).

  5. Add the Video Mixer IP and update the Streaming Video Format to YUV 4:2:2Video Series XX_3.png
  6. Add two AXI GPIOs to the design. We will use these to help control and monitor the design. 
  7. Name the two GPIO's "hls_ip_reset" and  "video_lock_monitor"

    To change the name of an IP, select the IP in IP Integrator and then update the name using the Block properties window.

    Video Series XX_4.png
  8. Configure "video_lock_monitor" for input and set its width to 1. Video Series XX_5.png
  9. Connect the locked output from the AXI4-Stream to Video out core to the input of "video_lock_monitor".



  10. Configure "hls_ip_reset"  for output and set its width to 1.Video Series XX65.png
  11. Connect the output of "hls_ip_reset" to the following reset pins:

    1. Video Mixer : ap_rst_n
    2. Video Test Pattern Generator: ap_rst_n
    3. AXI4-Stream to Video Out: aresetn



  12. Connect the Video Mixer AXI interconnect and processing system using the AXI_Interconnect_0.
    This will give the Video Mixer access to the DDR.Video Series XX11.png
  13. Connect the AXI-Stream ports of the TPG, Video Mixer, XI4-Stream Subset Converter, and the AXI4-Stream to Video out IPs as shown below.Video Series XX12.png
  14. Run Connection Automation and Select All.2019-10-09 17_23_23-xcoapps64_20 (xcoapps64_20 (samk)) - VNC Viewer.png


  15.   Connect the interrupt from the Video Mixer to the Processing System.                      Video Series XX14.png                
  16. Under the Address Editor tab, either auto-assign addresses or assign them by hand and make sure that they match the following. 

    Note: the addresses below only need to match if you want to use the test ELF provided. If not, you are free to assign the addresses as needed.   
    Video Series XX15.png
  17. Validate the BD, there should be no error. Save the BD.
  18. In the Sources Window, right-click again on the BD ( and click Create HDL Wrapper…2019-10-09 17_24_38-xcoapps64_20 (xcoapps64_20 (samk)) - VNC Viewer.png


  19. Select Let Vivado manage wrapper and auto-update 
  20. In the flow navigator, click on Generate Bitstream
  21. Once the bitstream is generated, export the Hardware Definition File (HDF) to be used in SDK by clicking on File > Export > Export Hardware…
  22. In the Export Hardware pop up window, enable "Include bitstream" and click OK

    This will create a .sdk directory with the HDF file inside. We will use this HDF file in the next Video Series entry.

  23. OPTIONAL - Test with the provided ELF (The ELF will be generated in the the next tutorial, Video Series 33)



Next Steps

For the Software required to run this hardware, please see Part 2 next week in Video Series 33.

To test your hardware, I have included the ELF file produced by Part 2 here.


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