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Vivado Design Entry Chronicles - IP Integrator Design Entry

Xilinx Employee
Xilinx Employee
0 0 232

This blog entry is the fourth lab in a series targeted at beginners in FPGA design entry using Vivado.

This lab covers design entry using IP Integrator.  Each step includes a screen shot for the user to refer to as they try it out.

Steps to follow:

1. Launch Vivado IDE.

2. In the Vivado GUI Click on Create Project:

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3. The New Project wizard will appear.

Provide the project name and the location where you want this project to be created, then click Next.

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4. Select RTL Project for the Project Type and Click Next.

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5. In Add Sources, you can Add RTL files to the project or create them. Click on Next (in this project we will be using IP Integrator).

6. In Add Constraints, you can add constraints files to the project. Click on Next (in this project we will be adding a .xdc file at a later stage).

7.In Default Part, you can select an FPGA part or board for your project.

Click on the Boards tab, search for ZCU102 and then select ZCU102 Evaluation Board. Click Next.

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8. In New project summary click on Finish.

9. In Flow Navigator click on Create Block Design under IP INTEGRATOR:

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10. The Create Block design Dialog box will appear. Provide the Block Design name of your choice and click OK.

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11. Click on the symbol in the Diagram window to add the IP to the Block design.

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12. In this IP Integrator Lab, we will be adding a Binary Counter IP to the Block Design. Search for Binary Counter and double click on it.

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13. The Binary counter IP block will appear in the Diagram window.

You can double click on the block to customize the IP (We are not customizing the IP in this lab).

14. Right click on the pins of the Binary counter IP block and click on Make External.

Do this on both the CLK and Q[15:0] pins. 

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15. Go to the sources window and right click on 'design_1' under Design sources, then select Create HDL Wrapper. 

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16. The Create HDL wrapper window will open. Choose 'Copy generate wrapper to allow user edits' and click ok.

The Top level RTL wrapper 'design_1_wrapper.v' will be generated.

Double click on it to open the file.

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17. Edit the design_1_wrapper.v file based on user configuration.

The RTL describes a simple free-running 16 bit counter. This 16 bit counter functionality is implemented using IP Integrator.

Once the counter reaches its max value, a flip-flop is toggled. This flop is connected to the output.

A differential Buffer is used (IBUFDS) to connect a differential pair of clocks whose output is used in the design. 

bd1.PNG

18. Click on Add Sources under Project Manager. 

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19. Click Add design constraints and click next:

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20. Click on add files and choose top.xdc and then click Finish.

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21. In Project Management Click on Generate bitstream.

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22. You might see the following prompt:

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Click on Yes.

A "Launch Runs" pop-up will appear. Click OK.

This will launch Synthesis followed by implementation, and generate the bitstream.

Our lab is now done.

 

XDC File Contents:

The XDC file contains the following:

create_clock -name clk_p -period 8 [get_ports clk_p]
set_property LOC G21 [get_ports clk_p]
set_property LOC AG14 [get_ports dout]

set_property IOSTANDARD LVCMOS18 [get_ports dout]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports clk_p]

 

Reason for use of IBUFDS:

The reason why we have used IBUFDS is that the board we have chosen requires a differential clock.

Each board will have its own specific pin LOCs and System Clock frequencies that it can support.

This board can support 300Mhz and 125Mhz, so we are using 125Mhz and the Pin LOC which corresponds to it. The output is connected to an LED which is LOC'ed at AG14. The last 2 statements are used to specify the IOSTANDARD for the ports.