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Vivado IP Upgrade Process – Example 2019.2 design to 2020.1.

aoifem
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Vivado IP Upgrade Process – Example 2019.2 design to 2020.1.

 

This Blog will outline the process of updating an IP core from one version to another. When done correctly the overhead of updating can be greatly reduced.

We will go through an example IP upgrade process from the 2019.2 version to the 2020.1 version.

 

Points to Note:

  • Xilinx only supports its IP library when matched with the correct version. For example, the 2019.2 HDMI core and 2019.2 Vivado. This is because the testing and qualification has been done using matching versions only. Customers can choose to use older IP in newer versions, but this flow is not supported through SRs or technical support.
  • Xilinx tests version to version upgrades, for example from 2019.1 to 2019.2. It is possible that there could be a problem with a 2017.1 to 2020.1 upgrade as this is not tested. In this case it might be easier to replace the IP vs upgrading using the GUI.
  • The driver version must always match the hardware version for the same testing and qualification reasons. In addition among other changes, register addresses and offsets can change from version to version of the IP.

 

Upgrade requirements: Drivers and Hardware

 

Things to know before starting:

  • Amount of effort required
    • For a larger version jump, more effort is likely required.
    • How can you figure out how much effort is required?
      • When upgrading across multiple versions, more effort is likely required as more might have changed within the IP or tools. 
      • Change logs document the changes to the IP. Xilinx releases a Master Change log AR each release. For example, (Xilinx Answer 73626).
        • Are there new or removed ports?
          • Updated ports might require an IP Integrator or RTL change.
        • Was there a change in the control logic to the core? (Reset/control/registers)
        • Were there new features added?
          • New features could require application or RTL modifications to access the features.
      • Git repo check-ins document driver changes. Baremetal drivers are provided with the Vivado install, but they along with Linux drivers can be found in the Xilinx GitHub
        • Was the API updated? (function calls changed, new functions added, structures modified)
          • If so, do I need to change my application?
          • If not, can I update in place?
      • Once the amount of effort is known and the tasks understood, it is much easier to upgrade.

 

Hardware Instructions

 

Example 1: Automatically Upgrading in Vivado

 

In this example I will show how to upgrade an IP from Vivado 2019.2 to 2020.1 (one version change).

  1. I have opened an example design for the ZCU106 board to illustrate how to do this. The example was initially saved as a project in Vivado 2019.2.  It contains the following IP:

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  1. Save your project in Vivado 2019.2, and close Vivado 2019.2. Open the project in Vivado 2020.1. When you open the project, the following prompt should pop up:

aoifem_1-1610477706452.png

 
  1. Select the option to ‘Automatically upgrade to the current version’. If successful, another pop-up screen should appear as below. Select ‘Report IP Status’:

aoifem_2-1610477715489.png

 
  1. A new ‘IP Status’ tab should appear at the bottom of the screen. The IP status tab shows you which IP have changes between Vivado 2019.2 and 2020.1. Selecting the ‘More Info’ line in the ‘change log’ column will show you what changes have been made to the IP in 2020.1.

aoifem_3-1610477732636.png

 

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5. Re-generate the output products when prompted. This will trigger the Vivado tools to store all IP customizations in the XCI file. The file is then used to produce the additional files needed during synthesis and simulation.

 

aoifem_6-1610477758439.png

 

Example 2: Removing and Replacing an IP. **Recommended for large upgrades such as 1 Year or greater.

 Xilinx only tests version to version upgrades. For example, 2019.1 to 2019.2. It is possible that there could be a problem with upgrading versions with more than 1 year of a difference between versions (e.g. 2017.1 to 2020.1) as this is not tested. In this case it might be easier to replace the IP vs upgrading using the GUI. The following steps explain how to do this:

  1. Open your old project version (in this case 2019.1) in the new version of the software (2020.1).
  2. Running the IP Status report will show the old IP that need updating, as before. Selecting a row in the ‘Source File’ column will highlight the appropriate IP in the block diagram that needs to be upgraded.

 

aoifem_8-1610477833288.png

 

  1. Delete this IP from the block diagram. Re-add the IP by right-clicking then selecting add IP -> search for the specific IP block.
    Please note, you might need to re-configure this IP block to match the configuration of the old IP. The IP will now be upgraded to 2020.1, and no longer needs to be updated.
  2. Re-run the IP status report to show that this IP no longer needs to be upgraded.

Software Instructions

 

Example 1: Generate a new BSP, and target the application at the new BSP.

 A Board Support Package (BSP) is a collection of drivers customized to the provided hardware description. Every application must be associated with a BSP. Often BSPs are created when an Application is created.

Let’s assume that you have exported an XSA from Vivado, and used it to create a software project in Vitis. If you later want to go back to Vivado to change your hardware design (either from upgrading you IP as explained above, changing your addresses/configuration, or otherwise altering the IP), you do not need to recreate your Vitis software project from scratch. However, you will need to make some alterations as explained below:

  1. Open your Vivado project, and make your alterations. In this example, we will change the address of axi_bram_ctrl_0 from 0xB000_0000 to 0xB000_1000. 
    This will simulate a change that could be possible when upgrading.
    It will also help us to validate that the XSA has been updated properly in the Vitis toolset.  

aoifem_9-1610477882488.png

  1. After your changes are made, re-run synthesis and implementation, and re-generate the bitstream.
    Export the new XSA file.

aoifem_10-1610477891713.png

  1. Open Vitis. We can check if the address is already updated by selecting the XSA file in the hw folder. Double clicking the IP name will allow you to view the IP parameters in detail:

 

aoifem_11-1610477900144.png

 

From the above screenshot, we can see that the address of the of axi_bram_ctl_0 is still the original address (0xB000_0000), so we know that the XSA file is out of date, and does not contain our hardware changes.

  1. To update the XSA, right-click on the platform project then select Update Hardware Specification. You will be prompted to select your updated XSA file.

aoifem_12-1610477909866.png

We can now see that the address has been updated, so our hardware changes in Vivado have been applied: 

aoifem_13-1610477920967.png

 Example 2: Regenerating the Project

Another option is to regenerate the BSP or platform project by hand. However, the flow in Example 1 is much simpler and is the recommended method for updating from one version to another.