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Vivado Timing Closure Techniques, Total Pulse Width Violation (TPWS) Part 2

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There are several types of timing violations that fall under the category of Pulse Width Violations.

    1.  Max Skew Violations (covered here)
    2.  Min Period Violations (covered in this blog)
    3. Max Period Violations
    4. Low Pulse Width Violations
    5. High Pulse Width Violations

The Pulse Width Violations are accounted for under the TPWS section of Report Timing Summary.

The worst of all of the Pulse Width violations are reported as the WPWS.

Capture3.PNG

For in-depth information about the pulse width violations, open the pulse width violation report in the Vivado GUI ( Select Reports -> Timing -> Report Pulse Width) or through the following Tcl command:

report_pulse_width

 

Min Period Violations:

This blog entry covers Min Period Violations only. 

Description of the report:

In the pulse width report, all clocks are checked for the minimum pulse width requirement.

      Capture4.PNG

Min Period Violation example:

As an example, this will be the report description when you open it in the GUI:

      Capture5.PNG

 

  • The above example shows the Min and Max period requirements for a particular clock.
    You can see that there is a negative slack for the Min period.
    This violation needs to be resolved to overcome the pulse width violation.

  • In this example, the Required value of 2.155ns and the Actual value of 1.250ns show the corresponding values for check type (Min Period). The Slack column shows the difference between them (Slack = Actual Value - Required Value).

 

Resolution:

  • In this example, the negative slack -0.905ns is on the input pin of the BUFG (Lib Pin: BUFG/I).
    To resolve this violation you will have to check the AC and DC characteristics of that particular device family, which will show the max permitted frequency for BUFG.
    As this is a silicon level limitation, you will need to tune down the frequency to resolve the violation.