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Vivado/Vitis 2020.2 - Zynq MPSoC Hello World to Versal ACAP Hello World

hj
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In this blog I will share the steps for running a Hello world on the industry first 7nm Versal ACAP devices. You will also learn about the similarities and differences between the Zynq® UltraScale+™ MPSoC, and Versal™ ACAP design flow. 

In this entry I will first run through the Zynq MPSoC flow, followed by the Versal ACAP flow.

 

Zynq MPSoC

Hardware Overview

Zynq UltraScale+ MPSoC is the Xilinx second-generation Zynq platform, combining a powerful processing system (PS) and user-programmable logic (PL) into the same device. 

The processing system features the Arm® flagship Cortex®-A53 64-bit quad-core or the dual-core processor and Cortex-R5F dual-core real-time processor.

 

System Block Diagram

     

hj_119-1614903247994.jpeg

 

Available Evaluation Boards

  ZCU102, ZCU104, ZCU106, ZCU111

Tools Support

Vivado, Vitis™

Documentation

1.Embedded Design Tutorial Link: https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/docs/Introduction/ZynqMPSoC-EDT

2.MPSoc Example Designs: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/444006775/Zynq+UltraScale+MPSoC

3. Technical Reference Manual https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

Video Walk-through Tutorials

Zynq Mpsoc Video Walk-through Tutorials

Processing System Block

Zynq MPSoC Block

  Project Wizard Settings 

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Create Block Design

hj_159-1614903843872.png
System Properties Settings
hj_161-1614904044271.png

Processing System IP

hj_162-1614904084786.jpeg

 

Step1: Click on the add IP or '+' button

Step2: Search Zynq MpSoC

Step3: Click OK to add the IP.  

IP Block Diagram

    

hj_164-1614904160117.jpeg

 

Block Automation

You will now use a preset template created for the ZCU102 board. Click the Run Block Automation Link. 

This configuration wizard enables many peripherals in the Processing System with some multiplexed I/O (MIO) pins assigned to them according to the board layout of the ZCU102 board. For example, UART0 and UART1 are enabled. The UART signals are connected to a USB-UART connector through UART to the USB converter chip on the
ZCU102 board.

hj_167-1614904222192.png

Validate Design

Right-click in the white space of the Block Diagram view and select Validate Design

Alternatively, you can press the F6 key.

Note:  A message dialog box will open and states "Validation successful. There are no errors or critical warnings in this design."

Generate Output Products

1. In the Block Design view, click the Sources tab.
        a. Click Hierarchy.
        b. Under Design Sources, right-click edt_zcu102 and select Create HDL Wrapper.

 2. Select Let Vivado Manage Wrapper and auto-update and click OK.
        a. In the Block Diagram, Sources window, under Design Sources, expand edt_zcu102_wrapper.
        b. Right-click the top-level block diagram, titled edt_zcu102_i : edt_zcu102 (edt_zcu102.bd) and select Generate Output Products.

3. Click Generate

 

Generate Device Image

 

Go to Flow Navigator→ Program and Debug and click Generate Device Bitstream. (.bit) 

 

hj_168-1614904588977.png

Export Hardware

To write a hardware platform using the GUI, follow these steps:

1. Select File → Export → Export Hardware in the Vivado Design Suite. The Export Hardware Platform window opens.
2. Select Platform Type as Fixed.
3. Click Next.
4. In the output window, select Include device bitstream and click Next.
5.Provide the XSA file name and Export path, then click Next

 6.Click Finish to generate the hardware platform file in the specified path.

hj_140-1614903248159.png

Build Software for PS Subsystems

1. Launch the Vitis IDE from the Windows start menu shortcut or by double-clicking the C:\Xilinx\Vitis\2020.1\bin\vitis.bat file.

2. Select the workspace and continue.

  hj_142-1614903248172.png

 

3. Select File → New → Application Project.

4. 4. Select Create from hardware specification (XSA). Browse the XSA file and provide the platform name. Click Next. 

hj_177-1614905180798.png

 

5. Provide the Application project name and select the Processor. Click Next. 

 Processor: psu_cortexa53_0

6. Select the Operating system and Architecture.

 Operating System: Standalone

 Architecture: 64-bit

7. Click Next

 

   

hj_178-1614905211801.jpeg

 

 

Application Template

Select the Hello World template. Click Finish. 

 

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Build Project

Now build the hardware by right-clicking Platform → Build Project.hj_181-1614905270220.png

 

hj_183-1614905304065.jpeg

 

Run Configuration

1. Right-click on the system project edt_zcu102 and select Run As → Run Configurations. The Run Configuration dialog box opens.

2. Double-click System Project Debug to create a Run Configuration.

3. Set the HW target as needed. 

4. Click Run.

 
hj_184-1614905377641.png

 

 

 

Versal ACAP

Hardware Overview

The Versal ACAP includes several processors, each with different computation capabilities to meet application needs. All devices, including the processing system (PS), the platform management controller (PMC), and the network on chip (NoC) interconnect to enable all processors to reach the DDR memory controllers and other resources within the device.

All Versal devices include programmable logic (PL). The Processing System includes an Arm Cortex-A72 dual-core processor along with the system memory management unit (SMMU) and the cache coherent interface (CCI) unit and Arm Cortex-R5F dual-core processor for applications requiring safety and deterministic execution times.

System Block Diagram

hj_120-1614903248014.jpeg

Available Evaluation Boards

 VCK190 ,VMK180

Tools Support

 Vivado, Vitis

Documentation

1. Embedded Design Tutorial Link: https://github.com/Xilinx/Embedded-Design-Tutorials/tree/2020.2/Versal-EDT

2. Versal Example Designs: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/487489537/Versal+Example+Designs

3. Technical Reference Manual https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf

Video Walk-through Tutorials

Versal Video Walk-through Tutorials

 Processing System Block

Versal ACAP Control, Interface and Processing IP (CIPS)

Project Wizard Settings 

hj_157-1614903756659.jpeg

Create Block Design

hj_158-1614903830874.png
System Properties Settings
hj_126-1614903248044.pnghj_127-1614903248049.jpeg

Processing System IP

hj_163-1614904104826.png

 

 Step1: Click on the add IP or '+' button

Step2: Search for CIPS 

Step3: Click OK to add the IP. 

IP Block Diagram

      

hj_165-1614904166623.jpeg

 

Block Automation

By default, the CIPS does not have any control or interfaces enabled. Applying the board preset enables those peripherals on the CIPS that have board connections to their MIO pins.

Double-click on CIPS IP, choose cips fixed io from the board tab as shown in the following figure & click OK.

 

 

hj_166-1614904217309.jpeg

Validate Design

Right-click in the white space of the Block Diagram view and select Validate Design

Alternatively, you can press the F6 key.

Note:  A message dialog box opens and states "Validation successful. There are no errors or critical warnings in this design."

Generate Output Products

1. In the Block Design view, click the Sources tab.
        a. Click Hierarchy.
        b. Under Design Sources, right-click edt_versal and select  Create HDL Wrapper.

 2. Select Let Vivado Manage Wrapper and auto-update and click OK.
        a. In the Block Diagram, Sources window, under Design Sources, expand edt_versal_wrapper.
        b. Right-click the top-level block diagram, titled edt_versal_i : edt_versal (edt_versal.bd) and select Generate Output Products.

3. Click Generate

Generate Device Image

Go to Flow Navigator→ Program and Debug and click Generate Device Image.(.pdi)

 

hj_169-1614904599274.png

Export Hardware

To write a hardware platform using the GUI, follow these steps: 

1. Select File → Export → Export Hardware in the Vivado Design Suite. The Export Hardware Platform window opens.
2. Select Fixed as the Platform Type.
3. Click Next.
4. In the output window, select the Include device image and click Next.
5.Provide the XSA file name and Export path, then click Next

6. Click Finish to generate the hardware platform file in the specified path.

hj_141-1614903248165.jpeg

Build Software for PS Subsystems

1.Launch the Vitis IDE from the Windows start menu shortcut or by double-clicking the C:\Xilinx\Vitis\2020.1\bin\vitis.bat file.

2.Select the workspace and continue.

 hj_174-1614905106466.png

 

3. Select File → New → Application Project.

4. Select Create from hardware specification (XSA). Browse to the XSA file and provide the platform name. Click Next. 


hj_175-1614905126590.jpeg

 

5. Provide the Application project name and select the Processor. Click Next. 

 Processor: psv_cortexa72_0

6. Select the Operating system and Architecture.

 Operating System: Standalone

 Architecture: 64-bit

 

7. Click Next.

 

hj_176-1614905155146.jpeg

Application Template

Select the Hello World template. Click Finish. 

 

hj_180-1614905249432.jpeg

 

Build Project

Now build the hardware by right-clicking Platform → Build Project.hj_181-1614905270220.png

 
hj_182-1614905300205.jpeg

 

Run Configuration

1. Right-click on the system project design_1_wrapper and select Run As → Run Configurations. The Run Configuration dialog box opens.

2. Double-click System Project Debug to create a Run Configuration.

3. Set the HW target as needed. 

4. Click Run

 
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