Xilinx PL and PS IBIS Model Decoders

samhendr · ‎07-22-2020

Xilinx provides I/O Buffer Information Specification (IBIS) models for all supported I/O standards in FPGA and MPSoC devices.

This blog entry provides a guide on how to decode an IBIS model name for both Programmable Logic (PL) and Processing System (PS) Multipurpose I/O (MIO).

This has been broken down into three sections.

PL I/O Standards
PS MIO Standards
PS DDR I/O Standards

In these sections you will find decoder tables which break down each part of the model name individually and then some example model names.

Xilinx PL I/O Standards IBIS Decoder

The PL IBIS Decoder can be used to decode PL IBIS models for all programmable logic I/Os. This applies to the Zynq MPSoC PL I/Os.

Table 1: PL IBIS Decoder

Xilinx PL IBIS Model Settings
Base Model	BANK-TYPE_IOSTANDARD_SLEW_OUTPUT-IMPEDANCE_INPUT-ODT_PRE-EMPHASIS OUTPUT-IMPEDANCE or OUTPUT-DRIVE-STRENGTH depending on IOSTANDARD
Model Setting	Options	Available Documentation
BANK-TYPE	HP, HR, HD	(UG571), Chapter 1, I/O Tile Overview
IOSTANDARD	See supported I/O standard for BANK-TYPE	HP and HR: (UG571), Chapter 1, Supported I/O Standards and Terminations HD: (UG571), Chapter 3, HD I/O Supported Standards
SLEW	FAST, MEDIUM, SLOW	(UG571), Chapter 1, Output Slew Rate Attributes
OUTPUT-IMPEDANCE (Ohm)*	40, 48, 60 or None	(UG571), Chapter 1, Source Termination Attribute (OUTPUT_IMPEDANCE)
OUTPUT-STRENGTH (mA)*	4, 8, 12 or 16	(UG571), Chapter 1, Output Drive Strength Attributes
INPUT-ODT (Ohm)	40, 48, 60, 120, 240 or None	(UG571), Chapter 1, On-Die Termination (ODT) Attribute
PRE-EMPHASIS	PE1600 or PE2400	(UG571), Chapter 1, Transmitter Pre-Emphasis

All models (except for LVDS*) will contain Bank Type, IOStandard, Slew Rate and Output Impedance/Drive Strength.

*LVDS models will contain Bank Type, LVDS IOStandard and Digital Termination.

Internal 100-ohm Differential Termination is only available in banks powered at 1.8V (LVDS) or 2.5V (LVDS_25). See (UG571), v1.12, p.130 for more details.

Note: not all model settings will be present in every IBIS model.

If a setting is not in the model name, that setting is not supported by the model.

Tables 2 and 3 provide examples of PL IBIS models for DDR4 and SelectIO.

Table 2: PL DDR4 IBIS Models

Example DDR4 IBIS Models
Signal Name	Model Name	Model Settings
DQ, DQS, DM	HP_POD12_DCI_F_OUT40_IN40_PE2400	Bank type: HP I/O Standard: POD Bank Voltage: 1.2V Digitally Controlled Impedance (DCI) Slew rate: Fast Output Impedance: 40 ohm Input ODT: 40 Ohm Pre-Emphasis enabled
Clock, Address & Command	HP_SSTL12_DCI_F_OUT40	Bank type: HP I/O Standard: SSTL Bank Voltage: 1.2V DCI Slew rate: Fast Output Impedance: 40 ohm

*Clock and DQS are differential signals. The single-ended models are assigned to each leg.

Differential signals are assigned in the IBIS file under the "[Diff Pin]" keyword.

Table 3: PL SelectIO IBIS Models

Example SelectIO IBIS Models
Model Name	Model Settings
HP_SSTL18_I_DCI_M_OUT40_IN60	Bank type = HP I/O Standard = SSTL_I Bank voltage = 1.8V Digitally Controlled Impedance Slew rate = Fast Output Impedance = 40 ohm Input ODT = 60 Ohm
HP_LVCMOS15_M_4	Bank type = HP I/O Standard = LVCMOS Bank voltage = 1.5V Slew rate = Medium Drive Strength = 4mA
HP_HSTL_I_F_OUT40	Bank type = HP I/O Standard = HSTL_I Bank voltage = 1.5V Slew rate = Fast Output Impedance = 40 ohm * This model is output only, with no DCI
HP_LVDS_DT_I	Bank type = HP I/O Standard = LVDS Bank voltage = 1.8V Differential Termination
HD_SSTL135_II_S_IN50	Bank type = HD I/O Standard = SSTL_II Bank voltage = 1.35V Slew rate = Slow Input ODT = 50 Ohm

Xilinx Zynq MPSoC PS MIO IBIS Models

The Zynq MPSoC MIO pins support LVCMOS with the following options

Interface voltage: 1.8V, 2.5V or 3.3V
Drive Strength: 2mA, 4mA, 8mA or 12mA
Slew Rate: Slow or Fast

The MIO IBIS model format is M0_PADH_02_F_NA_PBIDIR_18_18_NT_DR_H.

Table 4 explains the driver settings for each IBIS model.

Table 4: PS MIO IBIS Models

PS MIO IBIS Models
M0_PADH_02_F_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 2mA; Slew = Fast
M3_PADH_02_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 2mA; Slew = Slow
M6_PADH_04_F_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 4mA; Slew = Fast
M9_PADH_04_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 4mA; Slew = Slow
M12_PADH_08_F_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 8mA; Slew = Fast
M15_PADH_08_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 8mA; Slew = Slow
M18_PADH_12_F_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 12mA; Slew = Fast
M21_PADH_12_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 1.8V; Drive Strength = 12mA; Slew = Slow
M0_PADH_02_F_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 2mA; Slew = Fast
M3_PADH_02_S_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 2mA; Slew = Slow
M6_PADH_04_F_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 4mA; Slew = Fast
M9_PADH_04_S_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 4mA; Slew = Slow
M12_PADH_08_F_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 8mA; Slew = Fast
M15_PADH_08_S_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 8mA; Slew = Slow
M18_PADH_12_F_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 12mA; Slew = Fast
M21_PADH_12_S_NA_PBIDIR_25_25_NT_DR_H	LVCMOS 2.5V; Drive Strength = 12mA; Slew = Slow
M0_PADH_02_F_NA_PBIDIR_33_33_NT_DR_H	LVCMOS 3.3V; Drive Strength = 2mA; Slew = Fast
M3_PADH_02_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 3.3V; Drive Strength = 2mA; Slew = Slow
M6_PADH_04_F_NA_PBIDIR_33_33_NT_DR_H	LVCMOS 3.3V; Drive Strength = 4mA; Slew = Fast
M9_PADH_04_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 3.3V; Drive Strength = 4mA; Slew = Slow
M12_PADH_08_F_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 3.3V; Drive Strength = 8mA; Slew = Fast
M15_PADH_08_S_NA_PBIDIR_18_18_NT_DR_H	LVCMOS 3.3V; Drive Strength = 8mA; Slew = Slow
M18_PADH_12_F_NA_PBIDIR_33_33_NT_DR_H	LVCMOS 3.3V; Drive Strength = 12mA; Slew = Fast
M21_PADH_12_S_NA_PBIDIR_33_33_NT_DR_H	LVCMOS 3.3V; Drive Strength = 12mA; Slew = Slow

Xilinx Zynq MPSoC PS DDR IBIS Models

The Zynq MPSoC PS DDR IBIS signals are unique from all other signals.

Table 5 is a decoder for the Zynq MPSoC PS DDR IBIS models.

Examples of each DDR memory type IBIS model are provided.

Table 5: PS DDR IBIS Decoder

Zynq PS DDR IBIS Decoder
Base Model	DWC_D5MXY_Z_MS
X	I/O Type
C	Clock, Command, Control, Address
P	Data, Data Mask
Q	Data Strobe
Y	Memory Technology
3	DDR3
3L	DDR3L
L3	LPDDR3
4	DDR4
L4	LPDDR4
Z*	Output Impedance and/or Input Termination *Output and termination impedances are not adjustable on the PS DDR controller.
xx	Ouput impedance xx = 34 ohms (DDR4) xx = 40 ohms (DDR3, DDR3L, LPDDR3, LPDDR4)
ODTxx	input termination xx = 40 ohms (DDR3, DDR3L)
xxODTyy	Output Impedance with input termination (DDR4, LPDDR3 & LPDDR4) xx = 34 ohms (DDR4) xx = 40 ohms (LPDDR3) xx = 80 ohms (LPDDR4) yy = 40 ohms (DDR4, LPDDR4) yy = 120 ohms (LPDDR3)
MS	Model Selector
	The DQ and DQS models support the Model Selector feature. This is indicated by the "_MS" suffix. This will point the simulator to the [Model Selector] keyword in the IBIS file. The [Model Selector] keyword defines the ODT behavior.

Tables 6 through 10, Zynq PS DDR IBIS Examples are provided for supported PS DDR technologies.

Table 6: PS DDR3

DDR3
Signal Name	Model Name	Notes
PS_DDR3_CK_P/N (OUT)	DWC_D5MC3_40
PS_DDR3_A* (OUT)	DWC_D5MC3_40	Applies to Address, Command and Control
PS_DDR3_DQ* (IN/OUT)	DWC_D5MP3_ODT_MS	See Model Selector Example
PS_DDR3_DQS* (IN/OUT)	DWC_D5MQ3_ODT_MS	See Model Selector Example
Model Selector Example
DWC_D5MP3_ODT_MS	DWC_D5MP3_40 or DWC_D5MP3_ODT40
DWC_D5MQ3_ODT_MS	DWC_D5MQ3_40 or DWC_D5MQ3_ODT40

Table 7: PS DDR3L

DDR3L
Signal Name	Model Name	Notes
PS_DDR3L_CK_P/N (OUT)	DWC_D5MC3L_40
PS_DDR3L_A* (OUT)	DWC_D5MC3L_40	Applies to Address, Command and Control
PS_DDR3L_DQ* (IN/OUT)	DWC_D5MP3L_ODT_MS	See Model Selector Example
PS_DDR3L_DQS* (IN/OUT)	DWC_D5MQ3L_ODT_MS	See Model Selector Example
Model Selector Example
DWC_D5MP3L_ODT_MS	DWC_D5MP3L_40 or DWC_D5MP3L_ODT40
DWC_D5MQ3L_ODT_MS	DWC_D5MQ3L_40 or DWC_D5MQ3L_ODT40

Table 8: PS LPDDR3

LPDDR3
Signal Name	Model Name	Notes
PS_LPDDR3_CK_P/N (OUT)	DWC_D5MCL3_40
PS_LPDDR3_A* (OUT)	DWC_D5MCL3_40	Applies to Address, Command and Control
PS_LPDDR3_DQ* (IN/OUT)	DWC_D5MPL3_40ODT_MS	See Model Selector Example
PS_LPDDR3_DQS* (IN/OUT)	DWC_D5MQL3_40ODT_MS	See Model Selector Example
Model Selector Example
DWC_D5MPL3_40ODT_MS	DWC_D5MPL3_40 or DWC_D5MPL3_40ODT120
DWC_D5MQL3_40ODT_MS	DWC_D5MQL3_40 or DWC_D5MQL3_40ODT120

Table 9: PS DDR4

DDR4
Signal Name	Model Name	Notes
PS_DDR4_CK_P/N (OUT)	DWC_D5MC4_34
PS_DDR4_A* (OUT)	DWC_D5MC4_34	Applies to Address, Command and Control
PS_DDR4_DQ* (IN/OUT)	DWC_D5MP4_34ODT_MS	See Model Selector Example
PS_DDR4_DQS* (IN/OUT)	DWC_D5MQ4_34ODT_MS	See Model Selector Example
Model Selector Example
DWC_D5MP4_34ODT_MS	DWC_D5MP4_34 or DWC_D5MP4_34ODT40
DWC_D5MQ4_34ODT_MS	DWC_D5MP4_34 or DWC_D5MP4_34ODT40

Table 10: PS LPDDR4

LPDDR4
Signal Name	Model Name	Notes
PS_LPDDR4_CK_P/N (OUT)	DWC_D5MCL4_40
PS_LPDDR4_A* (OUT)	DWC_D5MCL4_40	Applies to Address, Command and Control
PS_LPDDR4_DQ* (IN/OUT)	DWC_D5MPL4_80ODT_MS	See Model Selector Example
PS_LPDDR4_DQS* (IN/OUT)	DWC_D5MQL4_80ODT_MS	See Model Selector Example
Model Selector Example
DWC_D5MPL4_80ODT_MS	DWC_D5MPL4_40 or DWC_D5MPL4_80ODT40
DWC_D5MQL4_80ODT_MS	DWC_D5MQL4_40 or DWC_D5MQL4_80ODT40

duditash · ‎12-28-2020

Hello,

I'm working on a new design, simulating by using the Hyperlynx 2.8 update 1, DDR wizard.

The Xilinx p/n is XCZU47DR-1FFVE1156I and its PS is connected to the LPDDR4 p/n MT53D512M32D2DS-046AATD ny MICRON.

The topology is point to point with 1.5inch traces, controlled inpledance according to the recommendation in the ug583-ultrascale-pcb-design.

The following are my questions:

1. Please explain the the DWC_D5MPL4_40 or DWC_D5MPL4_80ODT40 models.

a. for DWC_D5MPL4_40 - what does the 40 stand for, is it Pull-Up and series termination?

b. DWC_D5MPL4_80ODT40 - what do the 40 and 80 stand for?

2. I'm running many configuration with this LPDDR4 but I seem to fail each time. Please advise, what would be your recommended model to best fit the RFSOC?

(I'm not sure I understand thoroughly the LPDDR4 termination topologies).

Thank you in advance

Dudi