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Xilinx System Generator for DSP Chronicles - Generation of RTL Design

Xilinx Employee
Xilinx Employee
8 0 2,030

Xilinx System Generator for DSP provides a block diagram environment for model based design and a system integration platform that allows RTL, Simulink®, MATLAB® and C/C++ components of a DSP system to come together in a single simulation and implementation environment for Xilinx FPGA devices.

It is comprised of a predefined, optimized, ready-to-use block set for modeling, simulating and analyzing the Algorithms and generating the Test bench, Test vectors and finally the HDL code to accelerate FPGA development.

System Generator supports the following compilation targets for Automatic Code generation:

  • HDL Netlist
  • IP Catalog
  • Synthesized Checkpoint
  • Hardware Co-Simulation

Configuring MATLAB

Before we get started, we need to install MATLAB and make sure that MATLAB is configured for Vivado Design Suite.

This is done as follows:

On Windows:

Open (as Administrator) Start > All Programs > Xilinx Design Tools > Vivado 2019.x > System Generator > System Generator 2019.x MATLAB Configurator.

When the MATLAB configuration window appears, select the check box for the appropriate version of MATLAB.

Click Apply then OK.


On Linux:

We need to make sure that the MATLAB executable is found in the Linux system’s $PATH environment variable.

System Generator under Linux is handled using a shell script called sysgen located in the <Vivado_install_dir>/bin directory.

Steps to follow for the lab:

This blog entry is the first lab in a series which will be targeted at beginners who want to get started with Xilinx System Generator for DSP.

It provides a step by step approach to

  1. Model user Algorithms using the Xilinx System Generator block set
  2. Simulate the design and visualize the inputs/outputs to validate the design
  3. Generate the Test bench, Test vectors, and RTL (VHDL/Verilog) code for the design

The labs will be presented in the same order as the compilation targets specified above.

Step 1: Invoke System Generator following the step below for your OS:

  • On Windows systems, select Start > All Programs > Xilinx Design Tools > Vivado 2019.x >System Generator > System Generator 2019.x
  • On Linux Systems, type sysgen at the command prompt

This step opens the MATLAB session with the System Generator blockset.

It will look like the following screen capture:

step 1.png

Step 2: Change the working directory to any local directory where you want to create Sysgen models.

Click on the Simulink icon which is on the top right side of the MATLAB window.

This will open the Simulink Start Page:

step 2.png

Step 3: Click on the Blank model icon under the Simulink drop-down option.

This will open an Empty or Untitled model with a blank model canvas.

step 3.png

Step 4: Click on the Library browser icon in the Untitled model window to view the Xilinx block set in the Simulink Library Browser window.

Click and expand the Xilinx Blockset menu to view different categories of blocks. Click on the Basic elements category to view the basic sysgen blocks as shown below.

step 4.png

Step 5: Add the System generator token block to the model by right-clicking and selecting the "Add block to model" (Ctrl+I) option to define FPGA technology.

Similarly add Gateway In and Gateway Out blocks to define the boundary between the System Generator portion and the Simulink portion of the design.

Note:  These are the mandatory blocks that any model must consists of. A model needs to have at least one System Generator block and can have multiple Gateway In and Gateway Out blocks based on the inputs and outputs of the design.

step 5.png

Here we are modelling Mult-add operation so we need to add Mult, AddSub and Delay blocks to the model.

Step 6: Select the AddSub block from the Floating-Point category under Xilinx Blockset and right click on the block, then click the "Add block to model" option.

step 6.png

Step 7: Similarly add Mult block from the Floating-Point category under Xilinx Blockset and Delay block from the Basic Elements category to the model.

The model will look similar to the following:step 7.png

Step 8: Now add three instances of the constant block from the Sources category under the Simulink block set from the Simulink Library Browser:

step 8.png

Similarly add a Display block from the Sinks category under Simulink block set.

These blocks are used as stimulus for the System generator design.

Step 9: Connect the blocks by holding the left mouse button down and drawing a line from the source port to the destination port.

The complete model will look similar to the following:

step 9.png

Step 10: Double-click the Gateway In block to open the Properties Editor, set the input data type based on the input value under Output type and the Sample period in the block GUI, then Click OK.

Repeat the same process for other inputs:

step 10.png

Step 11: Double click on the System Generator token to change the system and simulation parameters.

Make sure that the Simulink system period under the clocking tab is the same as the sample period of the Gateway In blocks.

The FPGA clock period should be an integer multiple of the Simulink system period.

Click OK.

step 11.png

Step 12: Save the design by clicking on the save button in the model tool bar, give it a valid name and click on save (This step can be done anywhere between steps 3-9)

Step 13: Click the Run button to simulate the model and validate the output:

step 13.png

Step 14: Double click on the System Generator token and make sure of the following:

  • The Compilation is set to HDL Netlist
  • The target directory option is set to any valid directory where RTL code is getting generated (in this example it is netlist)
  • The Create testbench option on the Compilation tab is checked

For other options we will go with the default settings.

Now Click on Apply, then the Generate button.

step 14.png

Note: The System Generator token serves as a control panel for controlling system and simulation parameters, and it is also used to invoke the code generator.

Step 15: As soon as the code generation process starts, the status window pops up as shown below:

step 15.png

Step 16: Once code generation completes, the status window will notify you of the completion of the code generation process:

step 16.png

In the example from this screen capture, System generator has successfully generated the VHDL RTL design for a Kintex-7 xc7k325t-3fbg676 part including the test vectors and test bench.

Now launch Vivado, open the <Target directory>netlist/hdl_netlist/Multadd_test.xpr file and run through the Vivado flow as detailed in the blog entry below: