Design and Debug Techniques Blog

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Design and Debug Techniques Blog

txu
Xilinx Employee
Xilinx Employee

In the design cycle, users can have multiple versions of projects which use the same IPs with the same configurations. Rerunning the whole project can cause regeneration of the IPs every time, and is time-consuming.

In the Vivado project settings, the user IP repositories allow users to add their own IP to the Vivado IP catalog and when used alongside a Remote IP Cache, compile times can significantly reduce. This blog entry explains how to set this up.

You can find all of the entries in the Saving Compile Time Series here.

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bethf
Xilinx Employee
Xilinx Employee

This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal™ ACAP devices.  

It will additionally link you to relevant documentation, tutorials, and example designs. You can find all of our Versal related blogs here.

 

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