In the first 3 articles of the AI Engine Series, we went through the different files needed for an AI Engine application. In this entry we will run the AI Engine compiler for an X86 target and have a look at the different output it produces.
There are a host of IP cores available on the Versal™ Control, Interfaces and Processing System (CIPS) that users can access from the APU or RPU on the CIPS.
However, in this blog we will instead discuss how we can leverage these IP cores from a Soft Processor in the Programmable Logic. In this blog the Soft Processor will be the MicroBlaze. I will show how you how to execute from the PS DDR and how to leverage the UART on the CIPS.
There are also some neat tricks on how to modify the PDI to include a bootloop and custom CDO files that would have other application outside of the scope of this blog.