This blog provides an example on how a Python script can be used in debugging Xilinx PCIe designs. The script attached to this blog has been created with contribution from the community.

If you have already been using a similar approach to the one that is explained here or if you decide to use the provided script and enhance it further, we would be delighted if you could share your script with us and we will share it with the PCIe community members in this forum.

The provided technique can be applied to all designs and is not specific to PCIe only.

In this entry in the PetaLinux Image Debug Series we will discuss how we can debug the Zynq® UltraScale™ Linux Kernel images in Vitis™.

We will also cover how to use PetaLinux 2020.1 to create the Linux images for a Zynq UltraScale device. For all entries in this series, see here.

The analysis in this blog entry is based on a real customer issue where they were seeing poor QoR on one OS vs another. Although it was understood that Xilinx does not guarantee repeatability between different OS's as documented in (Xilinx Answer 61599), the magnitude of the difference in this case warranted further investigation.

Initially better results were seen with Windows, but later better results were seen with Linux. In the end, the issue was related to having certain Super Critical Methodology Violations in the design.

The Device Tree Generator (DTG) is a Tcl based utility that uses the HSI API to extract the hardware information from the XSA file to construct a custom device tree. The DTG utility is used in PetaLinux and Yocto. However, debugging DTG issues in PetaLinux can be cumbersome.

In this entry in the PetaLinux Image Debug Series we will discuss how we can isolate the DTG from PetaLinux, how to build the DTS files, how to navigate the DTG source files and how to debug a typical DTG issue. For all entries in this series, see here.