The Xilinxs Fast Fourier Transform (FFT) IP has a scaling feature to handle the bit growth in FFT output. This article provides insight into the scaling methods available in the IP and a method to select a scaling schedule to avoid overflow is discussed.
The analysis in this blog entry is based on a real customer issue where they were seeing DDR4 Calibration errors in hardware. The failures were inconsistent from one board to another and from build to build. This blog will show some of the debug techniques we used to narrow down the root cause and fix the issue.
This is part three of the Using the Methodology Report series. For all entries in the series, see here.