The analysis in this blog entry is based on a real customer issue where they were seeing rare bit flips in the field. This blog entry will show some of the debug techniques we used to narrow down the root cause and fix the issue.
In the end, the issue was caused by incorrect handling of clock domain crossing (CDC) which was highlighted by the report_methodology and report_cdc reports.
This is part four of the Using the Methodology Report series. For all entries in the series, see here.
This Blog covers how to use the AXI Interrupt Controller (INTC) in cases where you need to route more that 16 interrupts to the PS from IP cores in the PL. We are using Xilinx peripherals including GPIOs, IIC, UART and timers in the Vivado design.
The example design is created in the 2020.1 version of Vivado, targeting a ZCU106 evaluation board. Interrupts are tested on PetaLinux 2020.1, and the design Tcl and system-user.dtsi file are attached.