Design and Debug Techniques Blog

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Design and Debug Techniques Blog

deepeshm
Xilinx Employee
Xilinx Employee

The Versal™ ACAP Integrated Block for PCI Express® customization provides an option to enable PCIe® Link Debug.

Enabling this option will insert a debug core inside the IP core that will be recognized by the Vivado Hardware Manager and provide PCIe specific debug information and views.

The debug view provides information relating to the current link speed, current link width, and LTSSM state transitions, which can facilitate debug of PCIe link related issues.

 

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stephenm
Xilinx Employee
Xilinx Employee

MicroBlaze is a Soft Processor IP available in the Vivado IP catalog. There are various ways to debug the MicroBlaze.

This can be done in Vitis, or directly from the XSCT via the MDM.

In this blog we will discuss how to add an ILA to the MicroBlaze Instruction Trace port so that we can see in Hardware how the MicroBlaze is behaving.

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