Design and Debug Techniques Blog

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Design and Debug Techniques Blog

schuriw
Xilinx Employee
Xilinx Employee

This article explains how a sequential always block in Verilog code is interpreted by a Synthesis tool to determine the clock and any asynchronous control signals, along with their active values/polarity.

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ejanney
Xilinx Employee
Xilinx Employee

The Multirate Ethernet MAC (MRMAC) provides high-performance, low latency Ethernet ports supporting a wide range of customization and statistics gathering.  The MRMAC includes a variety of new features and design flows that enable seamless rate change, statistics management and integration with the GT blocks. 

This blog is intended to help customers with 100G Ethernet (CMAC) hard block or soft 10G/25G/40G or 50G Ethernet IP core experience to design efficiently with Versal™ MRMAC.  The blog will cover key differences between the UltraScale+ and Versal IP including:

  • Multi-Rate Considerations
  • AXI Stream Interface for Packet Data
  • New MRMAC Flex Port Feature
  • Statistics and Management 
  • 1588 PTP Support
  • Design Flow Considerations
  • Getting Started with the Versal MRMAC Example Design
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florentw
Moderator
Moderator

In the previous entry in the the AI Engine Series here, we ran AIE compiler to compile the graph and kernel codes to target the AI Engine model.

In this article we will have a look at the compilation summary file in Vitis™ Analyzer which gives us a lot of useful information about the compilation.

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syedz
Moderator
Moderator

In our previous blog entries, Improving QoR with report_qor_suggestions in Vivado and Design Closure with RQA and RQS, we learned how Report QOR Suggestions (RQS) helps in design closure with clocking, utilization, congestion and timing suggestions.

In this entry we cover the “RQS_CLOCK-12” clocking suggestion and how it helps in timing closure.

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