Design and Debug Techniques Blog

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Design and Debug Techniques Blog

deepeshm
Xilinx Employee
Xilinx Employee

A PL based PCIe base IP consists of PCIE PHY, GT QUAD and PCIe MAC. In addition to these, in QDMA/XDMA/Bridge IP cores, it consists of a corresponding additional wrapper module for the respective IP.

In PL PCIe for Versal ACAP, the way the PCIE IP as a whole is integrated with different components has changed compared to previous devices such as UltraScale and UltraScale+ devices.

The below are the major changes that went into PL based PCIe IP in Versal ACAP devices.

  • GT components are updated from Common/Channel to a quad granularity.
  • GT wizard flows are modified to use the Vivado® IP integrator.
  • Only the Vivado IP integrator-based block design flow is currently supported with manual or automatic connectivity.
  • The required GT and PHY IP blocks for Versal ACAP PL PCIe interfaces are outside of the Versal ACAP PL PCIE4 IP.

 

This blog illustrates the difference in the IP generation flow between Versal ACAP and UltraScale+ devices. 

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florentw
Moderator
Moderator

In previous entries in the AI Engine Series, we looked at the text files generated by the AIE simulator to do a functional verification of an AI Engine (AIE) application.

In this entry we will see how to generate traces to look at the state of the graph, which is one of the key elements of doing performance analysis.

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