This Blog covers how to use the AXI Interrupt Controller (INTC) in cases where you need to route more that 16 interrupts to the PS from IP cores in the PL. We are using Xilinx peripherals including GPIOs in the Vivado design.
The example design is created in the 2020.2 version of Vivado, targeting a VCK190 evaluation board. Interrupts are tested on PetaLinux 2020.2, and the design Tcl and system-user.dtsi file are attached.
This Blog entry is intended to illustrate an AXI DMA Linux user space example which sends data to the AXI Stream Data FIFO from the PS DDR and writes data on the PS DDR which is received from the AXI Stream Data FIFO.
In this blog I will share the steps for running the Hello world on industry first 7nm Versal ACAP devices. You will learn about the similarities and differences between the Zynq MPSoC and Versal ACAP design flow.