Design and Debug Techniques Blog

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Design and Debug Techniques Blog

Xilinx Employee
Xilinx Employee

The Xilinx PCI Express IP comes with the following integrated debugging features.

  • JTAG Debugger
  • Enable In-System IBERT
  • Descrambler in Gen3 Mode

The 'JTAG Debugger' provides the following information to assist in debugging PCI Express link training issues:

  • A graphical view of LTSSM states
  • A GUI based receiver detect status on all configured lanes
  • PHY RST state machine status

In-system IBERT provides the PCIe link Eye Diagram. The JTAG Debugger and the In-system IBERT features together provide instant information on the probable source of the link training issue.

Gen3 Mode Descrambler option provides a decoded interface of the PIPE data. It allows users to view the packets on the PCIe link. Details on this feature and how to decode the packet are available in this blog.


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