Design and Debug Techniques Blog

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Design and Debug Techniques Blog

savula
Moderator
Moderator

This Blog entry is intended to illustrate use of AXI DMA Simulation in Scatter Gather mode using AXI4 VIP cores and the AXI Stream VIP core.

 

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jbieker
Xilinx Employee
Xilinx Employee

This post provides a method to help designers determine if a given module can close timing in an empty die.  If a target module does not close timing out-of-context in an empty die, it is unlikely that it will close timing in-context with the rest of the design. Target modules can be extracted from the full design, floorplanned, constrained and then run through the implementation tool to determine whether or not timing closure can be achieved in a standalone fashion.

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