This blog entry covers how to debug Clock Domain Crossing issues in a design. It is based on a real customer design where timing was being met but the user was getting incorrect functionality on hardware.
(UG332) is the Spartan-3 Generation Configuration User Guide.
The User Guide does not cover the use-case of how to use an Internal Configuration Access Port (ICAP) to allow for a Multiboot application in a Spartan-3AN FPGA when booting from SPI Flash. We will cover that use-case in this Blog Entry.
Timing closure can be a challenging task in the FPGA design process. Underestimating the complexity of the task often leads to unrelenting schedule pressure. Xilinx provides many tools to help shorten timing closure, which allows for quicker product time to market. This blog post describes one method to reduce the effort of failing timing path analysis.