UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Design and Debug Techniques Blog

cancel
Showing results for 
Search instead for 
Did you mean: 

Design and Debug Techniques Blog

Moderator
Moderator

In Zynq UltraScale+ boards such as the Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit, the QSPI Flash is connected to the PS portion of the device and does not have a direct physical connection to the PL side.

In such configurations, it is not possible to write a bitstream (.mcs file) directly to the flash via the Hardware Manager. In fact, when attempting to configure the bitstream to be loaded via QSPI, Vivado will only make the Boot via JTAG option available, as it knows that there is no flash available in the PL.

In order to configure and boot such devices via Flash, the PS portion of the device must be booted (even if it is not desired or will not be used in the actual project), in order to allow the bitstream to be transmitted from the Flash to the PS and to reach the PL through the MIO pins.

The process consists of creating a new Zynq MPSoC project in Vivado Block Design (or adding this block to an existing design) in order to include the PS in the project, and using the SDK to create a First Stage Boot Loader (FSBL) for the PS, an optional PS application, and finally creating the flash image which will contain the boot files for both the PS and PL.

 

Read more...

Read more
3 0 312
Xilinx Employee
Xilinx Employee

This blog entry is the first lab in a series which will be targeted at beginners in FPGA design entry using Vivado.

These labs are organized to give the user a quick start and to help them to get a feel for how the tool flow works. We have picked a very simple design that is easy to understand so that different steps in the flow can be explained easily.

The labs will be presented in this order – RTL Flow, IP based Flow, HLS based Flow, IP Integrator based Flow, and then finally creating a design using a mix of the earlier flows.

Read more...

Read more
3 1 345