In the Versal AI Engine 2 article, we noticed a line in the graph file defining the run-time ratio parameter for each kernel instance.

In this article we will see how this parameter can impact the resource utilization and the performances of the AI Engine application.

In previous entries in the AI Engine Series, we looked at the text files generated by the AIE simulator to do a functional verification of an AI Engine (AIE) application.

In this entry we will see how to generate traces to look at the state of the graph, which is one of the key elements of doing performance analysis.

In the previous entry in the the AI Engine Series here, we ran AIE compiler to compile the graph and kernel codes to target the AI Engine model.

In this article we will have a look at the compilation summary file in Vitis™ Analyzer which gives us a lot of useful information about the compilation.

In the previous AI Engine Series article, we have run the AIE compiler targeting the X86 model and run the X86 simulator to verify the functional model of the AI Engine Application.

In this article we will run the AIE compiler targeting the AI Engine model and look at some of the generated outputs.

In the first 3 articles of the AI Engine Series, we went through the different files needed for an AI Engine application. In this entry we will run the AI Engine compiler for an X86 target and have a look at the different output it produces.

In the previous entry in the AI Engine Series, we had a look into the graph file which is the top level of the AI Engine application. We have seen how this graph file is used to instantiate and connect kernels together and to the ports of the AI Engine array.

In this entry we will look at the kernel. In the template we are looking at, the 2 kernels called first and second are implementing the same function which is called simple.

In the previous article, we had a first look at an AI Engine (AIE) application for Versal within the Vitis 2020.2 unified software platform.

We have seen the structure of an AIE application project and how an AIE graph is connected to a simulation platform. We also looked at some APIs to initialize, run and terminate the graph. In this article we will have a closer look at the AIE graph inside the project.

Last July, in the article titled Versal ACAP AI Engines for Dummies I introduced the AI Engine (AIE) array which is present in some Versal™ ACAP devices. In this new series of articles, the AI Engine Series, we will provide some examples of how to use the AI Engine tools integrated into the Vitis™ 2020.2 unified software platform.

This first article is an introduction to the AIE programming environment.

Versal^TM Adaptive Compute Acceleration Platforms (ACAPs) are the latest generation of Xilinx devices, built on the TSMC 7 nm FinFET process technology. They combine Scalar Engines (which represents the Processor System (PS)), Adaptable Engines (which represents the Programmable Logic (PL)), and Intelligent Engines which are connected together using a high-bandwidth network-on-chip (NoC). 

In this article, the focus is on the AI Engines which are part of the Intelligent Engines.