This blog demonstrates the use of Vivado ILA for debugging of a Versal™ ACAP in CPM Mode for PCI Express Designs designs.
The interface inside the CPM or the interface between the CPM and NOC cannot be probed using Vivado ILA as they are part of an integrated hard block. However, the interface between the NOC and the PL for the BRAM Controller can be probed using Vivado ILA.
This is particularly helpful as it allows you to monitor the incoming packets from a PCIe link or data being transferred from the PL region to the NOC and CPM and then finally to the link partner via a PCIe link.
This blog provides an example on how a Python script can be used in debugging Xilinx PCIe designs. The script attached to this blog has been created with contribution from the community.
If you have already been using a similar approach to the one that is explained here or if you decide to use the provided script and enhance it further, we would be delighted if you could share your script with us and we will share it with the PCIe community members in this forum.
The provided technique can be applied to all designs and is not specific to PCIe only.