Design and Debug Techniques Blog

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Design and Debug Techniques Blog

deepeshm
Xilinx Employee
Xilinx Employee

This blog demonstrates the use of Vivado ILA for debugging of a Versal™ ACAP in CPM Mode for PCI Express Designs designs.

The interface inside the CPM or the interface between the CPM and NOC cannot be probed using Vivado ILA as they are part of an integrated hard block. However, the interface between the NOC and the PL for the BRAM Controller can be probed using Vivado ILA.

This is particularly helpful as it allows you to monitor the incoming packets from a PCIe link or data being transferred from the PL region to the NOC and CPM and then finally to the link partner via a PCIe link.

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deepeshm
Xilinx Employee
Xilinx Employee

A PL based PCIe base IP consists of PCIE PHY, GT QUAD and PCIe MAC. In addition to these, in QDMA/XDMA/Bridge IP cores, it consists of a corresponding additional wrapper module for the respective IP.

In PL PCIe for Versal ACAP, the way the PCIE IP as a whole is integrated with different components has changed compared to previous devices such as UltraScale and UltraScale+ devices.

The below are the major changes that went into PL based PCIe IP in Versal ACAP devices.

  • GT components are updated from Common/Channel to a quad granularity.
  • GT wizard flows are modified to use the Vivado® IP integrator.
  • Only the Vivado IP integrator-based block design flow is currently supported with manual or automatic connectivity.
  • The required GT and PHY IP blocks for Versal ACAP PL PCIe interfaces are outside of the Versal ACAP PL PCIE4 IP.

 

This blog illustrates the difference in the IP generation flow between Versal ACAP and UltraScale+ devices. 

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deepeshm
Xilinx Employee
Xilinx Employee

The Versal™ ACAP Integrated Block for PCI Express® customization provides an option to enable PCIe® Link Debug.

Enabling this option will insert a debug core inside the IP core that will be recognized by the Vivado Hardware Manager and provide PCIe specific debug information and views.

The debug view provides information relating to the current link speed, current link width, and LTSSM state transitions, which can facilitate debug of PCIe link related issues.

 

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deepeshm
Xilinx Employee
Xilinx Employee

This blog provides an example on how a Python script can be used in debugging Xilinx PCIe designs. The script attached to this blog has been created with contribution from the community.

If you have already been using a similar approach to the one that is explained here or if you decide to use the provided script and enhance it further, we would be delighted if you could share your script with us and we will share it with the PCIe community members in this forum.

The provided technique can be applied to all designs and is not specific to PCIe only.

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