Design and Debug Techniques Blog

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Design and Debug Techniques Blog

txu
Xilinx Employee
Xilinx Employee

In the design cycle, users can have multiple versions of projects which use the same IPs with the same configurations. Rerunning the whole project can cause regeneration of the IPs every time, and is time-consuming.

In the Vivado project settings, the user IP repositories allow users to add their own IP to the Vivado IP catalog and when used alongside a Remote IP Cache, compile times can significantly reduce. This blog entry explains how to set this up.

You can find all of the entries in the Saving Compile Time Series here.

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txu
Xilinx Employee
Xilinx Employee

This blog entry introduces three powerful scripts which can help you to profile compile time for design implementation.

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txu
Xilinx Employee
Xilinx Employee

Incremental synthesis is a production feature since the 2019.1 release. It addresses the need for fast iterations during the synthesis phase, significantly reducing compile time while also ensuring predictable results, with no cost of QoR loss.

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txu
Xilinx Employee
Xilinx Employee

This blogs entry covers how to save compile time using the incremental implementation technique.

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txu
Xilinx Employee
Xilinx Employee

Compile time is always a key concern in design cycles. In this blog, we will cover the techniques for design compile time reduction, following the flow of design entry, synthesis, and implementation. This blog will be updated regularly, with more subtopics links added as they completed.

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