Design and Debug Techniques Blog

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Design and Debug Techniques Blog

Xilinx Employee
Xilinx Employee

Timing closure can be a challenging task in the FPGA design process.  Underestimating the complexity of the task often leads to unrelenting schedule pressure. Xilinx provides many tools to help shorten timing closure, which allows for quicker product time to market. This blog post describes one method to reduce the effort of failing timing path analysis.

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Xilinx Employee
Xilinx Employee

This post provides a method to help designers determine if a given module can close timing in an empty die.  If a target module does not close timing out-of-context in an empty die, it is unlikely that it will close timing in-context with the rest of the design. Target modules can be extracted from the full design, floorplanned, constrained and then run through the implementation tool to determine whether or not timing closure can be achieved in a standalone fashion.

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Moderator
Moderator

Welcome to the Vivado Timing Closure Techniques series.

In this series we will cover a number of types of timing violations that fall under the category of Pulse Width Violations.

This blog entry covers Max Skew Violations.

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Moderator
Moderator

Welcome to the Vivado Timing Closure Techniques series.

In this series we will cover a number of types of timing violations that fall under the category of Pulse Width Violations.

This blog entry covers Min Period Violations.

 

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