Design and Debug Techniques Blog

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Design and Debug Techniques Blog

hemangd
Moderator
Moderator

This blog entry covers how to debug a design which was an under-constrained, indirectly affecting the routability of the design.

The analysis in this blog entry is based on a real customer issue where their DFX design was not consistently routable and facing routing overlap.

This blog will show some of the debug techniques we used to narrow down the root cause and to fix the issue. 

This is part six of the Using the Methodology Report series. For all entries in the series, see here.

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viviany
Xilinx Employee
Xilinx Employee

The analysis in this blog entry is based on a real customer issue where they were seeing DDR4 post calibration data errors in hardware. The issue turned out to be timing related, but there was no violation in the timing report. The Methodology report was not the initial method used to pinpoint the root cause, but this blog will show you how this report would help to speed up the debug, or even to avoid the hardware failure.

This is part five of the Using the Methodology Report series. For all entries in the series, see here.

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dsheils
Moderator
Moderator

The analysis in this blog entry is based on a real customer issue where they were seeing rare bit flips in the field. This blog entry will show some of the debug techniques we used to narrow down the root cause and fix the issue. 

In the end, the issue was caused by incorrect handling of clock domain crossing (CDC) which was highlighted by the report_methodology and report_cdc reports.

This is part four of the Using the Methodology Report series. For all entries in the series, see here.

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dsheils
Moderator
Moderator

The analysis in this blog entry is based on a real customer issue where they were seeing DDR4 Calibration errors in hardware. The failures were inconsistent from one board to another and from build to build. This blog will show some of the debug techniques we used to narrow down the root cause and fix the issue. 

This is part three of the Using the Methodology Report series. For all entries in the series, see here.

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dsheils
Moderator
Moderator

The analysis in this blog entry is based on a real customer issue where they were seeing poor QoR on one OS vs another. Although it was understood that Xilinx does not guarantee repeatability between different OS's as documented in (Xilinx Answer 61599), the magnitude of the difference in this case warranted further investigation.

Initially better results were seen with Windows, but later better results were seen with Linux. In the end, the issue was related to having certain Super Critical Methodology Violations in the design.

 

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hemangd
Moderator
Moderator

This blog entry covers how to debug Clock Domain Crossing issues in a design. It is based on a real customer design where timing was being met but the user was getting incorrect functionality on hardware.

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