Design and Debug Techniques Blog

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Design and Debug Techniques Blog

stephenm
Moderator
Moderator

In this blog entry we will discuss how we can debug the Versal™ boot images such as the ATF and U-Boot (pre and post relocation) in Vitis™.

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stephenm
Moderator
Moderator

In this blog we will discuss how to debug the Platform Loader Manager (PLM) in Vitis.

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stephenm
Moderator
Moderator

Versal™ is an Adaptive Compute Acceleration Platform (ACAP) that is composed of a number of highly coupled configurable blocks. These blocks such as the NoC, AIE, PL, and CIPS (which itself has different domains; LPD, and FPD), all need to be configured at boot using the configuration set in Vivado.

With so many interconnecting blocks, this sounds complicated... but its not really. In this entry we will discuss these boot files, and how they are used.

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