Design and Debug Techniques Blog - Page 2

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Design and Debug Techniques Blog - Page 2

Moderator
Moderator

This blog entry is part one of our Simple Guide to Creating an Acceleration Platform for Vitis™. In this entry we will discuss how to enable your platform in the Vivado® Design Suite so that it is acceleration ready in Vitis.

Your platform can be an already established Vivado mature design that you would like to enhance to give you the flexiblity to accelerate software functions. Alternatively the platform can be a simple Vivado design that just has the topology needed for acceleration. The point being that the Vivado design used in the platform does not need to be a one-off design. It should be more organic, and change when your design needs to change.

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Moderator
Moderator

This is the second blog entry in the Acceleration Platform series.

Previously, we discussed how to create the hardware and how to pass the metadata to Vitis™ via the XSA.

In this entry we will discuss how to use this XSA and create the software images needed to accelerate your design on your target platform.

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Moderator
Moderator

This is the third blog entry in the Acceleration series. Previously, we discussed how to create the hardware and software projects. In this blog entry we will discuss how this is all packaged together in Vitis™.

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Moderator
Moderator

In the previous blog entries in this series we discussed how to create the hardware and software project. We then discussed how to package this project in Vitis™.

Next, we will be testing it in Vitis, by created a simple application that will be accelerated.

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Want to create your own IP with an AXI4-Lite interface, but unsure how to get started? This article will teach you the basics of how to create an AXI4-Lite interface in Vitis HLS using C code. 

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Moderator
Moderator

VersalTM Adaptive Compute Acceleration Platforms (ACAPs) are the latest generation of Xilinx devices, built on the TSMC 7 nm FinFET process technology. They combine Scalar Engines (which represents the Processor System (PS)), Adaptable Engines (which represents the Programmable Logic (PL)), and Intelligent Engines which are connected together using a high-bandwidth network-on-chip (NoC). 

In this article, the focus is on the AI Engines which are part of the Intelligent Engines.

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Xilinx Employee
Xilinx Employee

Xilinx provides I/O Buffer Information Specification (IBIS) models for all supported I/O standards in FPGA and MPSoC devices.

This blog entry provides a guide on how to decode an IBIS model name for both Programmable Logic (PL) and Processing System (PS) Multipurpose I/O (MIO).  This has been broken down into three sections.  

  1. PL I/O Standards
  2. PS MIO Standards
  3. PS DDR I/O Standards
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Xilinx Employee
Xilinx Employee

In data manipulation, it is typical to reshape or reorder the original data and create multiple copies. At any new step, a new copy is created. As the program grows, so does the occupied memory, and I seldom think to worry about this issue until an Out Of Memory error happens.

The amazing thing about tensors is that multiple tensors can refer to the same storage, allowing for much more efficient memory usage.

In the next article I will write about the even more amazing Tensor property of tracking the ancestors operations, but here I will mostly focus on memory optimization.

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Xilinx Employee
Xilinx Employee

We have learned through previous blog entries how Report QoR Assessment (RQA) and Report QoR Suggestions (RQS) can be used to improve the overall design analysis and timing closure experience of your design.

This blog entry will cover how to use RQA and RQS together in the implementation process using one specific design example.  

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Xilinx Employee
Xilinx Employee

This blog entry covers how to dynamically change UltraScale/UltraScale+ GTH/GTY transceiver line rate settings.

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Xilinx Employee
Xilinx Employee

Report QoR Assessment (RQA) details how likely you are to achieve your design’s QoR goals.

If the news back from the command is not what you were hoping for, this blog entry contains some additional information on what you can do next. This entry is great for new users of the commands, and should also be very handy for experienced users..

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Moderator
Moderator

On certain occasions, for example while working remotely, it might be necessary to access a device that is not locally available.

This brief tutorial demonstrates how to share and access a board which is in a remote Lab location, or in the possession of a co-worker.

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Xilinx Employee
Xilinx Employee

The Xilinx PCI Express IP comes with the following integrated debugging features.

  • JTAG Debugger
  • Enable In-System IBERT
  • Descrambler in Gen3 Mode

The 'JTAG Debugger' provides the following information to assist in debugging PCI Express link training issues:

  • A graphical view of LTSSM states
  • A GUI based receiver detect status on all configured lanes
  • PHY RST state machine status

In-system IBERT provides the PCIe link Eye Diagram. The JTAG Debugger and the In-system IBERT features together provide instant information on the probable source of the link training issue.

Gen3 Mode Descrambler option provides a decoded interface of the PIPE data. It allows users to view the packets on the PCIe link. Details on this feature and how to decode the packet are available in this blog.

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This blog entry guides you through how to use the FIR filter feature of the FIR compiler IP as a reloadable filter.

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Xilinx Employee
Xilinx Employee

This blog entry will show you how to create an AXI CDMA Linux userspace example application. The example design will transfer data from the PS DDR to the AXI BRAM through the AXI CDMA on a Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.

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Community Manager
Community Manager

Xilinx has a number of Online resources including Documentation, Answer Records, a Wiki, and the forums you are reading this blog entry on.

Which resource you should check first depends on the type of design you are working on and what stage of the design you are at.

This blog entry contains information on each of these resources and the best time to use them.

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This blog entry is intended to get you started with running Ethernet applications on our Xilinx® Versal™ ACAP VCK190 Evaluation Kit. It provides design creation steps for using the 2019.2 version of Vivado and Vitis to build and run Ethernet applications on a VCK190 board.

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Xilinx Employee
Xilinx Employee

This blog provides a list of videos showcasing the tutorials in (UG1209). The videos have been created using Vivado® Design Suite version 2019.1 and the Xilinx Software Development Kit (SDK). The examples are targeted for the Zynq® UltraScale+™ MPSoC ZCU102 Rev1 Evaluation Board.

Video 1 shows how to run an application using the ZCU102 board. While most of the videos run the applications using QEMU, the applications can also be run on the ZCU102 by following Video 1.

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Xilinx Employee
Xilinx Employee

This blog entry touches on how solving methodology issues will help you to make more effective timing closure decisions.

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Moderator
Moderator

If you are running the RF Data Converter IP simulation, you might have seen that it comes with its own simulation testbench.

This testbench can seem a little daunting. When trying to understand what is going on, there are many source files and it may not be clear where to even start. 

This Blog entry gives you a guide to how the IP example simulation can be used to check out the RF Data Converter. 

We'll  show you what the most important parts of the testbench are and how it is built ,and we'll also step through how it works.

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Xilinx Employee
Xilinx Employee

This blog entry provides a step by step video and links to associated documents with instructions for installing and running the QDMA Linux Kernel driver. It also provides some debug information.

It should be used in conjunction with the ‘read me’ file and documentation that comes with the driver. The QDMA Linux Kernel Driver can be downloaded from the link below:

https://github.com/Xilinx/dma_ip_drivers/tree/master/QDMA/linux-kernel

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Xilinx Employee
Xilinx Employee

XAPP1247 is an example application for Multiboot and Fallback when using Barrier Images. This Quick blog entry covers a method to test the barrier timer flow and an issue that can arise when doing so.

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In this new entry part of the AXI Basics series we look at how we can create an AXI Sniffer IP which can be used in Xilinx Vivado IP Integrator.

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In this fouth entry in the the AXI Basic Series, we will see an example of how to use the AXI protocol checker feature of the Xilinx AXI Verification IP (AXI VIP)

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This entry in the AXI Basics Series shows how the Xilinx AXI Verification IP can be used to simulate an AXI4-Lite master interface. We also look in detail at AXI4-Lite Read/Write transactions.

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Moderator

I2C is a serial protocol for two-wire interface to connect low-speed devices like EEPROMs, Sensors, RTC, ADC/DAC, and other compatible I/O interfaces in embedded systems. 

In this article, you will learn about the basics of Inter-Integrated Circuit (I2C or IIC) and usage of this protocol bus for short distance communcation.

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The Vivado Integrated Design Environment supports Universal Verification Methodology (UVM) when using Vivado Simulator.

This blog entry covers the steps to create a UVM example design in Vivado.

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Moderator
Moderator

Modern RF signal chains demand extremely high data converter performance across multiple channels. This means that for Xilinx RF Data Converters a key requirement is to have synchronization across multiple ADC/DAC tiles, RFSoC devices and even boards. 

Find out how Xilinx provides the solution to the Multi-Tile Synchronization problem to enable Beamforming, Massive MIMO and Phased Array Radar

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This blog entry covers the basics of configuring the device tree to add the details of external peripherals and third-party applications to a PetaLinux project.

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Xilinx Employee
Xilinx Employee

This blog entry is the first lab in a series which will be targeted at beginners who want to get started with Xilinx System Generator for DSP.

It provides a step by step approach to doing the following:

  • Model user Algorithms using the Xilinx System Generator block set
  • Simulate the design and visualize the inputs/outputs to validate the design
  • Generate Test bench, Test vectors and RTL (VHDL/Verilog) code for the design
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