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Design and Debug Techniques Blog - Page 2

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Design and Debug Techniques Blog - Page 2

Xilinx Employee
Xilinx Employee

UltraRAM primitives, also referred to as URAMs, are available in Xilinx UltraScale+™ Architecture and can be used to efficiently implement large and deep memory.

Typically such memories are not suitable for implementation using other memory resources due to their size and performance requirements.

The URAM primitives have configurable pipeline attributes in conjunction with dedicated cascade connections to enable high speed memory access.  Pipeline stages and cascade connections are configured using attributes on primitives. 

This blog entry describes methods for achieving optimal timing performance by configuring the URAM matrix to use pipeline registers.

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Moderator
Moderator

This blog is aimed at anyone who wants to get started with PetaLinux and learn about its key tools, concepts and capabilities. In the first blog entry, we will look at how to create a PetaLinux project, and how to modify an image. 

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Xilinx Employee
Xilinx Employee

This is part one of an ongoing series that covers how to debug PCIe Link Training Issues.

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Moderator
Moderator

RF Analyzer is a utility provided for use with the RF Data Converters in Zynq® UltraScale+™ RFSoC. 

Part one of this two part blog will show you how to build an RF Analyzer that can be deployed on any RFSoC device on any board. 

 

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Moderator
Moderator

The Video Processing Subsystem IP is an IP included for free in Vivado which supports multiple video processing features as Deinterlacing, Video Scaling (up and down scaling), Color Space Conversion, and Frame Rate.

This entry of the Video Series contains advice from Florent on how to start designing with this IP.

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Moderator
Moderator

The Xilinx Video Series covers a series of topics which help you learn how to use Xilinx Video IPs, as well as how to debug potential issues.

In this entry, Video Series number 26, we will see how the AXI Video Direct Memory Access (VDMA) IP can be used for applications such as video crop, picture in picture, or a soft pattern generator.

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Community Manager
Community Manager

You might have heard of IBIS Models and know that they are being used for Signal Integrity simulations, but aren't aware of how exactly these models are used.

If so, this blog post is for you.

In this entry we are going to use the Hyperlynx® tool and the IBIS models to go through a simple setup and run simulations. 

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Moderator
Moderator

The Synthesis process is divided into many phases, and based on which phase of synthesis the crash occurs in, the debugging steps can vary. This article covers the major crash areas and their respective debugging steps.

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Xilinx Employee
Xilinx Employee

A powerful feature of VHDL is the use of libraries to organize different sections of RTL.  By utilizing libraries, different designers can work on their own sections of the project without having to worry about naming conflicts with other designers.

This article covers the library called "work", which has a special usage in VHDL.

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Moderator
Moderator

So you are an RF Engineer working with our Amazing RF Data Converter Product and you want to get to grips with the software drivers?

Then this blog is for you. Let's kick-start your journey into the world of RFSoC embedded system software!

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Moderator
Moderator

The Xilinx Video Series covers a series of topics which help you learn how to use Xilinx Video IPs, as well as how to debug potential issues.

This entry, the 25th of the series, shows how to read the VDMA IPs status registers using the Xilinx Software Command Line Tool (XSCT) console in SDK, in order to detect possible root causes for errors happening with the AXI VDMA IP.

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Xilinx Employee
Xilinx Employee

SystemVerilog interfaces were developed to allow for easier connectivity between hierarchies in your design.  One way to think of them is as collections of pins that are common to many modules. Instead of having to define many pins on each module, they are defined once in an interface, and then the interface is defined on the module instead of pins.  If the set of signals is later changed, only the interface needs to change.

This allows a lot of information to be condensed into a smaller amount of lines, but it can be a little difficult to write for the first time. It can also be difficult to interpret an interface written by someone else when you are looking at it for the first time.  This article will explain the basics of interfaces and how to correctly write them in Vivado.

 

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Moderator
Moderator

 

The AXI Video Direct Memory Access (VDMA) IP allows a video stream from an AXI4-Stream interface to be moved to a memory. In this video series entry, we will show how to easily add the AXI VMDA IP in a video pipeline.

 

 

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Community Manager
Community Manager

Hello and welcome to part one of the hardware simulation blog series.

In this series we will review and explore the various Signal Integrity (SI) issues that affect today’s High-Speed Printed Circuit Board (PCB) designs and how to avoid them using simulation.

In this first entry we will look at the various models available for SI simulation, the differences between them, and which are preferrable when running an SI simulation.

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Moderator
Moderator

In this video series entry, we will create a design (Vivado design + SDK application) to generate a video output on the HDMI output connector of a PYNQ™-Z2 board.

This entry is a continuation of the Video Series from the Video board. You can see all previous entries in the Video series here.

 

 

 

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Xilinx Employee
Xilinx Employee

As frequency requirements continue to increase in complex FPGA designs, breaking the huge combinational logic and finding the optimal point for pipeline register insertion becomes more difficult. 

Register retiming techniques come in very useful in these situations.  This article will go into detail on the retiming feature within Vivado Synthesis.

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Moderator
Moderator

Welcome to the Xilinx Design and Debug Techniques blog, a new weekly blog where our Applications Engineers share their experiences and lessons learned designing and debugging with Xilinx.

This first entry is a continuation of the Video Series from the Video board. You can see all previous entries in the Video series here.

The Video Series will be published here from now on, along with entries from other Xilinx Engineers on their areas of expertise.

In the previous Video Series entry (Number 21), we created a design which sends a pattern (using the Test Pattern Generator (TPG) core) to the on-board HDMI of a Zynq®-7000 SoC ZC702 Evaluation Kit.

However, for this application, the resolution was fixed to 800x600p in the hardware design (there was no option to change it in the application).

In this Video Series entry we will see how to modify the hardware design and the application to support multiple video resolutions.

 

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