Design and Debug Techniques Blog - Page 2

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Design and Debug Techniques Blog - Page 2

ibaie
Xilinx Employee
Xilinx Employee

Embedded Linux development is split between the Linux image generation and the Linux application development. Xilinx provides PetaLinux tools for image generation and Vitis™ for the application development.
But how you can bring both tools together and develop applications for the Linux image generated with PetaLinux? This blog entry explores how to use the sysroot generated in PetaLinux in Vitis and develop Embedded Linux applications with libraries.

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wcassell
Administrator
Administrator

Welcome to our Design and Debug Techniques blog!

Scroll down to view posts chronologically, or click into this post for quick links to all of our Versal™ content and our ongoing series.

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sandrao
Community Manager
Community Manager

In the Versal™ families, the System Monitor is a part of the PMC block.

In this blog entry we will walk through an example of how to set up the System Monitor in the Control, Interfaces and Processor System (CIPS) Wizard in IP Integrator and read the values in the Vivado Hardware Manager.

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stephenm
Moderator
Moderator

In this quick-start demo we will discuss how to use the Git integration in Vitis™ and how to use the Team Actions so that Vitis Projects can be shared.

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samk
Moderator
Moderator

The UHD-SDI Subsystems RX/TX IP cores have several example designs available at the time of writing, but all are a variation of a pass-through design. For information on these designs, please see (PG289) and (PG290).

This Blog entry will instead outline how to create and run a TX only design targeting the ZCU106 development board.

 

 

 

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nathanx
Moderator
Moderator

This article is an introduction to debugging situations where a JESD204B link is down.

It goes through the information that needs to be gathered and possible causes of link synchronization failure.

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stephenm
Moderator
Moderator

Versal™ is an Adaptive Compute Acceleration Platform (ACAP) that is composed of a number of highly coupled configurable blocks. These blocks such as the NoC, AIE, PL, and CIPS (which itself has different domains; LPD, and FPD), all need to be configured at boot using the configuration set in Vivado.

With so many interconnecting blocks, this sounds complicated... but its not really. In this entry we will discuss these boot files, and how they are used.

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shabbirk
Moderator
Moderator

This blog covers the usage of the PetaLinux command-line to run QEMU with the PetaLinux BSP of a Versal™ ACAP and demonstrates a few of the networking options that QEMU supports.

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jhua
Xilinx Employee
Xilinx Employee

This blog entry covers a Versal GTY simulation example. It introduces the Master Reset Controller, demonstrates how GTY comes out of reset, and how to perform rate change.

 

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savula
Moderator
Moderator

This Blog entry is intended to illustrate how to access the AXI BRAM from the Versal™ APU through the NoC. 

The example design is created in the 2020.2 version of Vivado® and targets a VCK190 evaluation board. The Tcl script for this design and application code are available in the attachments to this blog entry.

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hemangd
Moderator
Moderator

The Methodology report is a feature in the Vivado tool which helps to streamline the design process and achieve better QoR using the UltraFast Design Methodology (UFDM).

This blog entry gives some background on this report and the UFDM and also links to six related blog entries which contain examples of how the Methodology Report helps to improve Design QoR and saves you time in debugging the root cause of an issue.

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stephenm
Moderator
Moderator

This blog will discuss how to use Python to create some cool apps and utilities targeting IP cores on Zynq UltraScale devices.

A package is supplied here that you can use to read the devicetree and access IP cores. There is also a useful utility to read the PHY registers, and toggle LEDs.

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hemangd
Moderator
Moderator

This blog entry covers how to debug a design which was an under-constrained, indirectly affecting the routability of the design.

The analysis in this blog entry is based on a real customer issue where their DFX design was not consistently routable and facing routing overlap.

This blog will show some of the debug techniques we used to narrow down the root cause and to fix the issue. 

This is part six of the Using the Methodology Report series. For all entries in the series, see here.

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viviany
Xilinx Employee
Xilinx Employee

The analysis in this blog entry is based on a real customer issue where they were seeing DDR4 post calibration data errors in hardware. The issue turned out to be timing related, but there was no violation in the timing report. The Methodology report was not the initial method used to pinpoint the root cause, but this blog will show you how this report would help to speed up the debug, or even to avoid the hardware failure.

This is part five of the Using the Methodology Report series. For all entries in the series, see here.

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stephenm
Moderator
Moderator

PetaLinux is a great utility that allows designers to easily create Linux images to run on their target platforms. PetaLinux will also create user applications and modules with a template Makefile and BB files so that they can be built and added to a rootfs.

However, for users trying to develop a module, creating, building, and deploying from the command line speeds up the process.

In this blog entry we will discuss how to create a module and then build and deploy it on a ZCU104 board outside of the PetaLinux flow. Once users are content that the module is working, they can then add it to the rootfs.

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dsheils
Moderator
Moderator

The analysis in this blog entry is based on a real customer issue where they were seeing rare bit flips in the field. This blog entry will show some of the debug techniques we used to narrow down the root cause and fix the issue. 

In the end, the issue was caused by incorrect handling of clock domain crossing (CDC) which was highlighted by the report_methodology and report_cdc reports.

This is part four of the Using the Methodology Report series. For all entries in the series, see here.

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abhinayp
Xilinx Employee
Xilinx Employee

This Blog covers how to use the AXI Interrupt Controller (INTC) in cases where you need to route more that 16 interrupts to the PS from IP cores in the PL. We are using Xilinx peripherals including GPIOs, IIC, UART and timers in the Vivado design. 

The example design is created in the 2020.1 version of Vivado, targeting a ZCU106 evaluation board. Interrupts are tested on PetaLinux 2020.1, and the design Tcl and system-user.dtsi file are attached.

 

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vkanchan
Xilinx Employee
Xilinx Employee

The Xilinxs Fast Fourier Transform (FFT) IP has a scaling feature to handle the bit growth in FFT output. This article provides insight into the scaling methods available in the IP and a method to select a scaling schedule to avoid overflow is discussed.

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dsheils
Moderator
Moderator

The analysis in this blog entry is based on a real customer issue where they were seeing DDR4 Calibration errors in hardware. The failures were inconsistent from one board to another and from build to build. This blog will show some of the debug techniques we used to narrow down the root cause and fix the issue. 

This is part three of the Using the Methodology Report series. For all entries in the series, see here.

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deepeshm
Xilinx Employee
Xilinx Employee

This blog provides an example on how a Python script can be used in debugging Xilinx PCIe designs. The script attached to this blog has been created with contribution from the community.

If you have already been using a similar approach to the one that is explained here or if you decide to use the provided script and enhance it further, we would be delighted if you could share your script with us and we will share it with the PCIe community members in this forum.

The provided technique can be applied to all designs and is not specific to PCIe only.

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stephenm
Moderator
Moderator

In this entry in the PetaLinux Image Debug Series we will discuss how we can debug the Zynq® UltraScale™ Linux Kernel images in Vitis™.

We will also cover how to use PetaLinux 2020.1 to create the Linux images for a Zynq UltraScale device. For all entries in this series, see here.

 

 

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dsheils
Moderator
Moderator

The analysis in this blog entry is based on a real customer issue where they were seeing poor QoR on one OS vs another. Although it was understood that Xilinx does not guarantee repeatability between different OS's as documented in (Xilinx Answer 61599), the magnitude of the difference in this case warranted further investigation.

Initially better results were seen with Windows, but later better results were seen with Linux. In the end, the issue was related to having certain Super Critical Methodology Violations in the design.

 

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nishak
Moderator
Moderator

The Device Tree Generator (DTG) is a Tcl based utility that uses the HSI API to extract the hardware information from the XSA file to construct a custom device tree. The DTG utility is used in PetaLinux and Yocto. However, debugging DTG issues in PetaLinux can be cumbersome.

In this entry in the PetaLinux Image Debug Series we will discuss how we can isolate the DTG from PetaLinux, how to build the DTS files, how to navigate the DTG source files and how to debug a typical DTG issue. For all entries in this series, see here.

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gguasti
Xilinx Employee
Xilinx Employee

This is part three of the Object Oriented Dataset with Python and PyTorch blog series.

For Part One, see here. For Part two see here.

In this entry we repeat the procedure we just completed in part two on a Cat and Dog database, and we will add something else.

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gguasti
Xilinx Employee
Xilinx Employee

This is part two of the Object Oriented Dataset with Python and PyTorch blog series. For Part One, see here.

We defined the MyDataset class in Part One, now let's instantiate a MyDataset object.

 

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gguasti
Xilinx Employee
Xilinx Employee

A very common problem in Machine Learning is deciding how best to interface with data.

In this article we present an elegant method to interface with, organize, and then eventually transform the data (preprocessing). We will then cover how to properly feed the model during training procedures.

 

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hemangd
Moderator
Moderator

This blog entry covers how to debug Clock Domain Crossing issues in a design. It is based on a real customer design where timing was being met but the user was getting incorrect functionality on hardware.

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ddn
Xilinx Employee
Xilinx Employee

(UG332) is the Spartan-3 Generation Configuration User Guide.

The User Guide does not cover the use-case of how to use an Internal Configuration Access Port (ICAP) to allow for a Multiboot application in a Spartan-3AN FPGA when booting from SPI Flash. We will cover that use-case in this Blog Entry.

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bfell
Xilinx Employee
Xilinx Employee

Timing closure can be a challenging task in the FPGA design process.  Underestimating the complexity of the task often leads to unrelenting schedule pressure. Xilinx provides many tools to help shorten timing closure, which allows for quicker product time to market. This blog post describes one method to reduce the effort of failing timing path analysis.

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stephenm
Moderator
Moderator

In this blog entry we will discuss how we can debug the Zynq UltraScale device boot images in Vitis. These boot images include the ARM Trusted Firmware (ATF) and U-boot.

Boot image debug is a vital part of any custom board bring up, and hopefully this blog will allow users to fully debug a custom board  boot image. Even if you are using a development board, this blog will provide a useful insight into how the boot images work on Zynq UltraScale. For all entries in this series, see here.

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