This post provides a method to help designers determine if a given module can close timing in an empty die. If a target module does not close timing out-of-context in an empty die, it is unlikely that it will close timing in-context with the rest of the design. Target modules can be extracted from the full design, floorplanned, constrained and then run through the implementation tool to determine whether or not timing closure can be achieved in a standalone fashion.
In the "IIC Protocol and Programming Sequence" blog entry, we provided a detailed explanation for beginners of the Inter-Integrated Circuit (IIC) protocol basics and programming sequences. In this blog entry, we will discuss self debug techniques for AXI IIC and PS IIC.
The lspci and setpci commands are available natively in Linux distributions. This command has various levels of output, and provides a very useful point-in-time look at the capabilities and status of the different components trained on the PCI bus.
Most of these capabilities are reflections of the Configuration Space registers required by the PCI Express Base Specification. As with most commands, usage instructions can be found by running "lspci --help" or "man lspci", in Linux.
The RoE (Radio Over Ethernet) IP provides two simulation example flows, the Block Automation flow and the Open IP Example Flow. This article provides a tutorial for both flows, and shows users how to use the demo testbench to control IP configurations.
This blog entry is part one of our Simple Guide to Creating an Acceleration Platform for Vitis™. In this entry we will discuss how to enable your platform in the Vivado® Design Suite so that it is acceleration ready in Vitis.
Your platform can be an already established Vivado mature design that you would like to enhance to give you the flexiblity to accelerate software functions. Alternatively the platform can be a simple Vivado design that just has the topology needed for acceleration. The point being that the Vivado design used in the platform does not need to be a one-off design. It should be more organic, and change when your design needs to change.
This is the third blog entry in the Acceleration series. Previously, we discussed how to create the hardware and software projects. In this blog entry we will discuss how this is all packaged together in Vitis™.
VersalTM Adaptive Compute Acceleration Platforms (ACAPs) are the latest generation of Xilinx devices, built on the TSMC 7 nm FinFET process technology. They combine Scalar Engines (which represents the Processor System (PS)), Adaptable Engines (which represents the Programmable Logic (PL)), and Intelligent Engines which are connected together using a high-bandwidth network-on-chip (NoC).
In this article, the focus is on the AI Engines which are part of the Intelligent Engines.
In data manipulation, it is typical to reshape or reorder the original data and create multiple copies. At any new step, a new copy is created. As the program grows, so does the occupied memory, and I seldom think to worry about this issue until an Out Of Memory error happens.
The amazing thing about tensors is that multiple tensors can refer to the same storage, allowing for much more efficient memory usage.
In the next article I will write about the even more amazing Tensor property of tracking the ancestors operations, but here I will mostly focus on memory optimization.
We have learned through previous blog entries how Report QoR Assessment (RQA) and Report QoR Suggestions (RQS) can be used to improve the overall design analysis and timing closure experience of your design.
This blog entry will cover how to use RQA and RQS together in the implementation process using one specific design example.
Report QoR Assessment (RQA) details how likely you are to achieve your design’s QoR goals.
If the news back from the command is not what you were hoping for, this blog entry contains some additional information on what you can do next. This entry is great for new users of the commands, and should also be very handy for experienced users..
The Xilinx PCI Express IP comes with the following integrated debugging features.
Enable In-System IBERT
Descrambler in Gen3 Mode
The 'JTAG Debugger' provides the following information to assist in debugging PCI Express link training issues:
A graphical view of LTSSM states
A GUI based receiver detect status on all configured lanes
PHY RST state machine status
In-system IBERT provides the PCIe link Eye Diagram. The JTAG Debugger and the In-system IBERT features together provide instant information on the probable source of the link training issue.
Gen3 Mode Descrambler option provides a decoded interface of the PIPE data. It allows users to view the packets on the PCIe link. Details on this feature and how to decode the packet are available in this blog.
This blog entry will show you how to create an AXI CDMA Linux userspace example application. The example design will transfer data from the PS DDR to the AXI BRAM through the AXI CDMA on a Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit.
This blog entry is intended to get you started with running Ethernet applications on our Xilinx® Versal™ ACAP VCK190 Evaluation Kit. It provides design creation steps for using the 2019.2 version of Vivado and Vitis to build and run Ethernet applications on a VCK190 board.
This blog provides a list of videos showcasing the tutorials in (UG1209). The videos have been created using Vivado® Design Suite version 2019.1 and the Xilinx Software Development Kit (SDK). The examples are targeted for the Zynq® UltraScale+™ MPSoC ZCU102 Rev1 Evaluation Board.
Video 1 shows how to run an application using the ZCU102 board. While most of the videos run the applications using QEMU, the applications can also be run on the ZCU102 by following Video 1.