Design and Debug Techniques Blog

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Design and Debug Techniques Blog

pthakare
Moderator
Moderator

This blog entry covers important information users should consider when using Embedded Memory/FIFO Generator and XPM_MEMORY/FIFO in designs targeted for Versal™ ACAPs.

It also includes links to relevant references, test designs and test benches.

 

 

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abhinayp
Xilinx Employee
Xilinx Employee

This Blog covers how to use the AXI Interrupt Controller (INTC) in cases where you need to route more that 16 interrupts to the PS from IP cores in the PL. We are using Xilinx peripherals including GPIOs in the Vivado design. 

The example design is created in the 2020.2 version of Vivado, targeting a VCK190 evaluation board. Interrupts are tested on PetaLinux 2020.2, and the design Tcl and system-user.dtsi file are attached.

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savula
Moderator
Moderator

This Blog entry is intended to illustrate an AXI DMA Linux user space example which sends data to the AXI Stream Data FIFO from the PS DDR and writes data on the PS DDR which is received from the AXI Stream Data FIFO.

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hj
Moderator
Moderator

In this blog I will share the steps for running the Hello world on industry first 7nm Versal ACAP devices. You will learn about the similarities and differences between the Zynq MPSoC and Versal ACAP design flow. 

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florentw
Moderator
Moderator

In the Versal AI Engine 2 article, we noticed a line in the graph file defining the run-time ratio parameter for each kernel instance.

In this article we will see how this parameter can impact the resource utilization and the performances of the AI Engine application.

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abommera
Xilinx Employee
Xilinx Employee

This Versal™ example design will show how to run AXI DMA standalone application example on a VCK190 evaluation board and is intended to demonstrate use of the AXI DMA standalone driver which is available as part of Vivado and Vitis™.

In this blog, we will discuss how to run an AXI DMA bare-metal application to make use of DMA standalone driver in the 2019.2 release. To quick test with design files in the 2020.2 version, refer to this AXI DMA GitHub Example.

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deepeshm
Xilinx Employee
Xilinx Employee

A PL based PCIe base IP consists of PCIE PHY, GT QUAD and PCIe MAC. In addition to these, in QDMA/XDMA/Bridge IP cores, it consists of a corresponding additional wrapper module for the respective IP.

In PL PCIe for Versal ACAP, the way the PCIE IP as a whole is integrated with different components has changed compared to previous devices such as UltraScale and UltraScale+ devices.

The below are the major changes that went into PL based PCIe IP in Versal ACAP devices.

  • GT components are updated from Common/Channel to a quad granularity.
  • GT wizard flows are modified to use the Vivado® IP integrator.
  • Only the Vivado IP integrator-based block design flow is currently supported with manual or automatic connectivity.
  • The required GT and PHY IP blocks for Versal ACAP PL PCIe interfaces are outside of the Versal ACAP PL PCIE4 IP.

 

This blog illustrates the difference in the IP generation flow between Versal ACAP and UltraScale+ devices. 

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florentw
Moderator
Moderator

In previous entries in the AI Engine Series, we looked at the text files generated by the AIE simulator to do a functional verification of an AI Engine (AIE) application.

In this entry we will see how to generate traces to look at the state of the graph, which is one of the key elements of doing performance analysis.

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stephenm
Moderator
Moderator

In this blog entry we will discuss how we can debug the Versal™ boot images such as the ATF and U-Boot (pre and post relocation) in Vitis™.

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stephenm
Moderator
Moderator

In this blog we will discuss how to debug the Platform Loader Manager (PLM) in Vitis.

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schuriw
Xilinx Employee
Xilinx Employee

This article explains how a sequential always block in Verilog code is interpreted by a Synthesis tool to determine the clock and any asynchronous control signals, along with their active values/polarity.

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ejanney
Xilinx Employee
Xilinx Employee

The Multirate Ethernet MAC (MRMAC) provides high-performance, low latency Ethernet ports supporting a wide range of customization and statistics gathering.  The MRMAC includes a variety of new features and design flows that enable seamless rate change, statistics management and integration with the GT blocks. 

This blog is intended to help customers with 100G Ethernet (CMAC) hard block or soft 10G/25G/40G or 50G Ethernet IP core experience to design efficiently with Versal™ MRMAC.  The blog will cover key differences between the UltraScale+ and Versal IP including:

  • Multi-Rate Considerations
  • AXI Stream Interface for Packet Data
  • New MRMAC Flex Port Feature
  • Statistics and Management 
  • 1588 PTP Support
  • Design Flow Considerations
  • Getting Started with the Versal MRMAC Example Design
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florentw
Moderator
Moderator

In the previous entry in the the AI Engine Series here, we ran AIE compiler to compile the graph and kernel codes to target the AI Engine model.

In this article we will have a look at the compilation summary file in Vitis™ Analyzer which gives us a lot of useful information about the compilation.

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syedz
Moderator
Moderator

In our previous blog entries, Improving QoR with report_qor_suggestions in Vivado and Design Closure with RQA and RQS, we learned how Report QOR Suggestions (RQS) helps in design closure with clocking, utilization, congestion and timing suggestions.

In this entry we cover the “RQS_CLOCK-12” clocking suggestion and how it helps in timing closure.

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deepeshm
Xilinx Employee
Xilinx Employee

The Versal™ ACAP Integrated Block for PCI Express® customization provides an option to enable PCIe® Link Debug.

Enabling this option will insert a debug core inside the IP core that will be recognized by the Vivado Hardware Manager and provide PCIe specific debug information and views.

The debug view provides information relating to the current link speed, current link width, and LTSSM state transitions, which can facilitate debug of PCIe link related issues.

 

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stephenm
Moderator
Moderator

MicroBlaze is a Soft Processor IP available in the Vivado IP catalog. There are various ways to debug the MicroBlaze.

This can be done in Vitis, or directly from the XSCT via the MDM.

In this blog we will discuss how to add an ILA to the MicroBlaze Instruction Trace port so that we can see in Hardware how the MicroBlaze is behaving.

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florentw
Moderator
Moderator

In the previous AI Engine Series article, we have run the AIE compiler targeting the X86 model and run the X86 simulator to verify the functional model of the AI Engine Application.

In this article we will run the AIE compiler targeting the AI Engine model and look at some of the generated outputs.

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klumsde
Moderator
Moderator

In Gen 3 of Zynq UltraScale+ RFSoC devices, programming the CLK104 module can be done via the System Controller UI, but this blog shows you how you can also boot the CLK104 PLLs over I2C/SPI from the RFSoC APU.

We have a driver that makes this possible by taking the I2C and SPI communications and abstracting them so that you just need to worry about what settings you want to program. This driver can also be used for Linux Applications, giving you more possibilities for prototyping on the RFSoC Gen3 Evaluation Boards,. 

This blog also takes a look at the new Gen3 Clock Distribution options as part of our CLK104 programming example. 

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florentw
Moderator
Moderator

In the first 3 articles of the AI Engine Series, we went through the different files needed for an AI Engine application. In this entry we will run the AI Engine compiler for an X86 target and have a look at the different output it produces.

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aoifem
Moderator
Moderator

This Blog will outline the process of updating an IP core from one version to another. When done correctly the overhead of updating can be greatly reduced.

 

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stephenm
Moderator
Moderator

There are a host of IP cores available on the Versal™ Control, Interfaces and Processing System (CIPS) that users can access from the APU or RPU on the CIPS.

However, in this blog we will instead discuss how we can leverage these IP cores from a Soft Processor in the Programmable Logic. In this blog the Soft Processor will be the MicroBlaze. I will show how you how to execute from the PS DDR and how to leverage the UART on the CIPS.

There are also some neat tricks on how to modify the PDI to include a bootloop and custom CDO files that would have other application outside of the scope of this blog.

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txu
Xilinx Employee
Xilinx Employee

In the design cycle, users can have multiple versions of projects which use the same IPs with the same configurations. Rerunning the whole project can cause regeneration of the IPs every time, and is time-consuming.

In the Vivado project settings, the user IP repositories allow users to add their own IP to the Vivado IP catalog and when used alongside a Remote IP Cache, compile times can significantly reduce. This blog entry explains how to set this up.

You can find all of the entries in the Saving Compile Time Series here.

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bethf
Xilinx Employee
Xilinx Employee

This blog entry will cover important information you should understand before designing with Memory Interfaces on Versal™ ACAP devices.  

It will additionally link you to relevant documentation, tutorials, and example designs. You can find all of our Versal related blogs here.

 

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florentw
Moderator
Moderator

In the previous entry in the AI Engine Series, we had a look into the graph file which is the top level of the AI Engine application. We have seen how this graph file is used to instantiate and connect kernels together and to the ports of the AI Engine array.

In this entry we will look at the kernel. In the template we are looking at, the 2 kernels called first and second are implementing the same function which is called simple.

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florentw
Moderator
Moderator

In the previous article, we had a first look at an AI Engine (AIE) application for Versal within the Vitis 2020.2 unified software platform.

We have seen the structure of an AIE application project and how an AIE graph is connected to a simulation platform. We also looked at some APIs to initialize, run and terminate the graph. In this article we will have a closer look at the AIE graph inside the project.

 

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florentw
Moderator
Moderator

Last July, in the article titled Versal ACAP AI Engines for Dummies I introduced the AI Engine (AIE) array which is present in some Versal™ ACAP devices. In this new series of articles, the AI Engine Series, we will provide some examples of how to use the AI Engine tools integrated into the Vitis 2020.2 unified software platform.

This first article is an introduction to the AIE programming environment.

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aravindb
Moderator
Moderator

In this blog entry we will demonstrate how to boot Linux from a USB secondary boot on a Versal AI Core Series VCK190 Evaluation Kit.

To do this we will modify the Boot Image Format (BIF) to load a second Programmable Device Image (PDI) via USB using the 2020.2 release of the tools.

 

 

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sandrao
Community Manager
Community Manager

This Blog entry is intended for new users of the Versal™ Advanced IO Wizard. It gives an introduction to setting up the Wizard and some insights into running a simulation. 

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stephenm
Moderator
Moderator

In this Blog we will discuss how we can execute a MicroBlaze™ Application from the PSU DDR on a Zynq UltraScale ZCU104 board.

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eschidl
Xilinx Employee
Xilinx Employee

To create a transceiver setup for several quads for Versal it is recommended to start with the transceiver bridge IP, choose your settings there and then let Vivado create the necessary quads for this setup through block automation.

The bridge IP allows for only one setup. So, how is it possible to have separate setups for TX and RX in the same transceiver?

This blog entry contains some examples of how to do this.

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