05-25-2016 10:41 AM - edited 05-25-2016 10:44 AM
Running Vivado 2015.4 on Win 7
Used DDS Compiler core to generate a simple sine LUT with 16 bit input and 14 bit output
Line from XCI:
But it generartes a LUT with 16 bit outputs as shown in the VHO and the elaboration error I get.
VHO Line: m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
Error: [Synth 8-549] port width mismatch for port 'm_axis_data_tdata': port width = 16, actual width = 14
A 14 bit signal is connected to m_axis_data_tdata.
Regenerated it a couple times. Same result. I got nothin... For the moment, I guess I can just truncate the two LSBs.
05-25-2016 01:12 PM
So I attached a 16 bit signal to the output and probed into the schematic to find this:
So it's 14 bits internally, but gets wrapped by "i_synth" with a 16 bit port. That can't be right.
06-07-2016 01:37 PM - edited 06-07-2016 01:37 PM
Alas, it is.
AXI spec requires tdata width to be byte multiples. 14 bits are all that's needed based on the requirements for the core configuration, but the next widest byte multiple is 16, thus the 16 bit width. Internally, the core just strips off unused bits (so just tie them to ground).
This is standard procedure for AXI IPs.