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Contributor
Posts: 37
Registered: ‎08-07-2008

DDS Compiler SINE LUT output width mismatch

[ Edited ]

Running Vivado 2015.4 on Win 7

 

Used DDS Compiler core to generate a simple sine LUT with 16 bit input and 14 bit output

 

Untitled.png

 

Line from XCI:

<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTPUT_WIDTH">14</spirit:configurableElementValue>
     

But it generartes a LUT with 16 bit outputs as shown in the VHO and the elaboration error I get.

VHO Line: m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

Error: [Synth 8-549] port width mismatch for port 'm_axis_data_tdata': port width = 16, actual width = 14

 

A 14 bit signal is connected to m_axis_data_tdata.

 

Regenerated it a couple times. Same result. I got nothin... For the moment, I guess I can just truncate the two LSBs.

 

Contributor
Posts: 37
Registered: ‎08-07-2008

Re: DDS Compiler SINE LUT output width mismatch

So I attached a 16 bit signal to the output and probed into the schematic to find this:

 

Untitled.png

 

So it's 14 bits internally, but gets wrapped by "i_synth" with a 16 bit port. That can't be right.

Xilinx Employee
Posts: 3,597
Registered: ‎08-02-2011

Re: DDS Compiler SINE LUT output width mismatch

[ Edited ]

Hello,

 

Alas, it is.

 

AXI spec requires tdata width to be byte multiples. 14 bits are all that's needed based on the requirements for the core configuration, but the next widest byte multiple is 16, thus the 16 bit width. Internally, the core just strips off unused bits (so just tie them to ground).

 

This is standard procedure for AXI IPs.

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