We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Posts: 1
Registered: ‎12-24-2015

Xilinx HDMI 1.4/2.0 RX Subsystem



I need to get access to native video in this subsystem rather than axi4 stream video provided.


I have seen AR# 57546 which shows you how to modify/edit IP core source files in Vivado but I have been unsuccessful in being able to merge the top level changes to output the HDMI_RX video out signals (HS, VS, Video_data(71:0), DE) at the top level instead of the axi4s video signals.


I can produce a static IP version of the IP from the IP Catalog. I can make the required changes to bd_0_vhd and the wrapper to connect the required signals to the top level but I can't get to a point where I can edit and merge in the IP packager. I can't instatiate the IP from the catalog at the RTL level it always gives me the board design files.


Why aren't both the native and AXI4S video output signals provided in this IP? How do I get to the native video output?