04-19-2018 08:30 PM
Here is a question regarding AXI Quad SPI v3.2 IP in Vivado 2017.4
I am driving the ip with a state machine.
In simulation, I see that a read returns the reset value of the register addr 0x60 value = 0x180 as expected, but an attempted write does not work because the AWREADY stays low. I have attached a screenshot of a simulation waveform showing the successful read and the stalled write. I am also attaching a screenshot of the vivado configuration of the IP. I am quite sure I have wired the fsm together correctly, but just in case, I have copied and pasted the instantiations of the two modules in a code snippet below.
Any help would be appreciated!
assign ext_spi_clk = sys_clk;
assign s_axi_aclk = sys_clk;
assign s_axi_aresetn = ~sys_rst;
//for now tie the inputs of the tri states to zero
assign io0_i = '0;
assign io1_i = '0;
assign ss_i = '0;
04-24-2018 06:58 AM
04-24-2018 06:58 AM
04-24-2018 10:47 AM
That indeed solved the issue.
Is this always the necessary protocol for AXI Lite?
I was using an AXI burst write example from the ARM protocol spec (diagram attached) ... shows awvalid going high before wvalid.
04-24-2018 12:51 PM
I agree with you; I don't think this should be required according to spec. But I've seen it before with other cores :).
From my recollection of studying the matter, I believe it may be an ambiguity in the spec. One note on the subject is:
The dependency rules must be observed to prevent a deadlock condition. For example, a master must not
wait for AWREADY to be asserted before driving WVALID. A deadlock condition can occur if the slave is
waiting for WVALID before asserting AWREADY.
However, I could see the argument for interpreting the situation as: The master is not waiting for awready; it simply doesn't have data ready yet so can't assert wvalid. Then again... if it happens indefinitely, it's probably waiting on awready and thus a violation.
09-16-2018 05:47 PM
Set the awvalid and wvalid at the same time , but awready/wready keep 0 , so strange , where is the problem?