08-15-2018 12:18 PM - edited 08-15-2018 12:21 PM
I have studied the TRM and I am still perplexed about whether I can use QSPI0 and QSPI1 as two independent QSPI ports post boot and if so, how do I tell Linux in the device tree that is what I am doing.
Specifically, I want to boot from QSPI0 in Single SS, 4 bit mode. That should happen automatically because, according to the TRM, the configuration logic will read QSPI0, find the necessary sentinel bits and start the boot sequence without going to QSPI1 at all (at least, that is how I understood it).
Then, if that works, I want to access QSPI1 as a separate memory at run time. But I don't see how to define the device tree to distinguish QSPI0 and QSPI1.
I am starting to believe the only way to accomplish this is to go to Dual SS, 4 bit stacked-IO mode but I see conflicting capability indications in the TRM like this:
Each side of the dual controller port can be individually enabled or operate together as an 8-bit I/O
interface. (Section 12.5.3)
Can anyone illuminate me?
08-17-2018 06:58 AM
QSPI is designed to be used 1 of 3 ways, QSPI single, QSPI dual-parallel or QSPI dual-stacked. For Dual-Parallel operation, Xilinx software assumes the parts are used together to create an 8-bit data bus. From what you described for your design goals, I would suggest QSPI dual-stacked, which creates a linear QSPI address space, use only the lower QSPI for boot and map the upper QSPI for your application needs.
08-22-2018 11:38 AM
Thanks for your response. So the sentence in the TRM that states that:
Each side of the dual controller port can be individually enabled (Section 12.5.3)
is incorrect and should be deleted?
08-22-2018 01:09 PM
The controller allows for separate control, the Xilinx provided software does not. You are more than welcome to write your own driver to use the QSPI devices independently.