UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer willchenyx
Observer
239 Views
Registered: ‎12-18-2018

Can Ultrascale + MPSOC load and configure the PL before PS, or How to load and configure PL as soon as possible?

Jump to solution
AS our board is a PCIe endpoint, the PL must load and configure as soon as possible. If configure the PL until Kernel is loaded, its too late, the PC cannot recognise our PCIe endpoint(We run Linux on MPSOC).
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
228 Views
Registered: ‎09-01-2014

Re: Can Ultrascale + MPSOC load and configure the PL before PS, or How to load and configure PL as soon as possible?

Jump to solution

If you use Kernel to program PL, it won’t meet 100ms PCIe requirement.

You can use FSBL to program PL. it can meet 100ms.

The fastest boot device is QSPI, so you need to set SCLK to 150MHz and change XFSBL_PS_DDR flag in xfsbl_partition_load.c to skip loading bitstream to PL.

Here is the result we measured on ZCU106 using Tandem PROM bitstream with the change above.

You can see 1st stage Done only takes around 40ms, if you don't need to make 2nd stage under 100ms, only boot from QSPI at 150MHz is enough.

pcie.JPG

 

Tags (1)
3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
229 Views
Registered: ‎09-01-2014

Re: Can Ultrascale + MPSOC load and configure the PL before PS, or How to load and configure PL as soon as possible?

Jump to solution

If you use Kernel to program PL, it won’t meet 100ms PCIe requirement.

You can use FSBL to program PL. it can meet 100ms.

The fastest boot device is QSPI, so you need to set SCLK to 150MHz and change XFSBL_PS_DDR flag in xfsbl_partition_load.c to skip loading bitstream to PL.

Here is the result we measured on ZCU106 using Tandem PROM bitstream with the change above.

You can see 1st stage Done only takes around 40ms, if you don't need to make 2nd stage under 100ms, only boot from QSPI at 150MHz is enough.

pcie.JPG

 

Tags (1)
Observer willchenyx
Observer
188 Views
Registered: ‎12-18-2018

Re: Can Ultrascale + MPSOC load and configure the PL before PS, or How to load and configure PL as soon as possible?

Jump to solution

Hi, Ritakur

Thanks for your reply!

One more question, how can I set SCLK to 150MHz?

The picture below is my setting of PS. Is that mean my  SCLK is 300MHz??(According to what i know, the usual frequency of SCLK is 100MHz)

搜狗截图20190628102926.png

0 Kudos
Moderator
Moderator
171 Views
Registered: ‎03-19-2014

Re: Can Ultrascale + MPSOC load and configure the PL before PS, or How to load and configure PL as soon as possible?

Jump to solution

To set the QSPI device frequency, refer to AR69381

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos