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Debugging the PL and PS side at the same time

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Explorer
Posts: 137
Registered: ‎04-19-2016

Debugging the PL and PS side at the same time

[ Edited ]

Hello,

 

I am currently using the JTAG of Zynq SoC in independent JTAG mode, which is the PS side JTAG connection through PJTAG pins and PL side debugging (ILA) through PL side JTAG pins. In this schema, I have used two connectors.

 

Could I use a JTAG scan bridge IC for debugging PS and PL side at the same time, through one main JTAG port? 

Does it make sense to connect the PL JTAG pins to one port of the scan bridge IC and the PS JTAG pins to another port of the scan bridge IC? Can it be used like this?

 

Please see attached JTAG chain drawing below.

 

Best Regards,

srl.png
Xilinx Employee
Posts: 102
Registered: ‎10-11-2011

Re: Debugging the PL and PS side at the same time

Which debugger are you using to debug the processor? Lauterbach can debug PS and (using Vivado) PL from the same connector.

http://www2.lauterbach.com/pdf/int_vivado.pdf