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Explorer
Explorer
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Debugging the PL and PS side at the same time

Hello,

 

I am currently using the JTAG of Zynq SoC in independent JTAG mode, which is the PS side JTAG connection through PJTAG pins and PL side debugging (ILA) through PL side JTAG pins. In this schema, I have used two connectors.

 

Could I use a JTAG scan bridge IC for debugging PS and PL side at the same time, through one main JTAG port? 

Does it make sense to connect the PL JTAG pins to one port of the scan bridge IC and the PS JTAG pins to another port of the scan bridge IC? Can it be used like this?

 

 

Best Regards,

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Xilinx Employee
Xilinx Employee
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Re: Debugging the PL and PS side at the same time

Which debugger are you using to debug the processor? Lauterbach can debug PS and (using Vivado) PL from the same connector.

http://www2.lauterbach.com/pdf/int_vivado.pdf

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Explorer
Explorer
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Re: Debugging the PL and PS side at the same time

Hello,

 

I have used ARM DS-5 Dstream debugger. We cannot debug PS and PL side at the same time, if we dont use two different connectors for each side JTAG port. So, we need to take Zynq into the independent JTAG mode. But I dont think that it is needed to connect PL and PS side JTAG ports to the scan bridge IC, separately. Because, only Zynq TAP side(PL) has boundary-scan capability for entire Zynq IC. DAP is only debug purpose for ARM side(PS).

 

Thank you, 

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