07-09-2018 09:04 AM - edited 07-11-2018 07:17 AM
I am currently using the JTAG of Zynq SoC in independent JTAG mode, which is the PS side JTAG connection through PJTAG pins and PL side debugging (ILA) through PL side JTAG pins. In this schema, I have used two connectors.
Could I use a JTAG scan bridge IC for debugging PS and PL side at the same time, through one main JTAG port?
Does it make sense to connect the PL JTAG pins to one port of the scan bridge IC and the PS JTAG pins to another port of the scan bridge IC? Can it be used like this?
Please see attached JTAG chain drawing below.
07-13-2018 01:03 PM
Which debugger are you using to debug the processor? Lauterbach can debug PS and (using Vivado) PL from the same connector.