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Explorer
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Registered: ‎04-21-2017

Zynq PJTAG connection as two signal svs Tristate

Dear Forum,

I’m trying to use the PJTAG port in the Vivado Block Design window.  I can turn on the PJTAG EMIO feature, and it gives me four lines, TCK, TMS, TDI and TDO.  The problem is that the TDO line is a three-state line and I really need it to be a pair of signals instead (TDO and TDO_ENABLE).  Looking at the device view of a synthesised design, I can see that the PS block inside the FPGA has separate TDO and TDO_ENABLE ports, but there is no apparent way to get Vivado to present these to me separately. 

Do you have any magic inside knowledge that will give me access to these ports?

 

Regards,

DJE666

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