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Visitor brinda_wh
Visitor
76 Views
Registered: ‎12-05-2018

qspi boot problem

hi

I've designed a custom board based on the zedboard.i made a simple helloworld project and run it in sdk successful

to save it in QSPI flash(FL128SAIF00 SPANSION), i add FSBL to sdk project & make boot.mcs file.

I changed boot mode to JTAG.

SPI_DQ0/MODE0=PullDown(20K)

SPI_DQ1/MODE1=PullDown(20K)

SPI_DQ2/MODE2=PullDown(20K)

SPI_DQ3/MODE3=PullDown(20K)

SPI_SCK/MODE4=PullDown(20K)

These messages are displayed when the programs are running in sdk console

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-JTAG-SMT2-210251A08870
	Device 0: jsn-JTAG-SMT2-210251A08870-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info:  Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B




U-Boot 2018.01-00071-g0018654-dirty (May 01 2018 - 11:18:16 -0600)



Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Silicon: v3.1

DRAM:  256 KiB

WARNING: Caches not enabled

Using default environment



In:    dcc

Out:   dcc

Err:   dcc

Zynq> sf probe 0 0 0


SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB

Zynq> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 400000


SF: 4194304 bytes @ 0x0 Erased: OK

Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 11 sec.
Performing Blank Check Operation...
0%...sf read FFFC0000 0 10000
.
.
.
. Zynq> INFO: [Xicom 50-44] Elapsed time = 23 sec. Blank Check Operation successful. The part is blank. Performing Program Operation... 0%...sf write FFFC0000 0 20000 device 0 offset 0x0, size 0x20000 SF: 131072 bytes @ 0x0 Written: OK Zynq> sf write FFFC0000 20000 20000 . . . . . device 0 offset 0x3f0000, size 0x5248 SF: 21064 bytes @ 0x3f0000 Read: OK Zynq> cmp.b FFFC0000 FFFD0000 5248 Total of 21064 byte(s) were the same Zynq> INFO: [Xicom 50-44] Elapsed time = 22 sec. Verify Operation successful. Flash Operation Successful

 

I changed boot mode to QSPI

SPI_DQ0/MODE0=PullDown(20K)

SPI_DQ1/MODE1=PullDown(20K)

SPI_DQ2/MODE2=PullDown(20K)

SPI_DQ3/MODE3=PullUp(20K)

SPI_SCK/MODE4=PullDown(20K)

.But FPGA will not be DONE.How to solve this problem?????????????

 

 

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3 Replies
Moderator
Moderator
60 Views
Registered: ‎03-19-2014

Re: qspi boot problem

I would start with AR59174 and run the standalone QSPI test software 

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Visitor brinda_wh
Visitor
37 Views
Registered: ‎12-05-2018

Re: qspi boot problem

I reviewed this page

1) Is the QSPI flash and configuration supported by Xilinx?

yes,I checked it.my QSPI part is (S25FL128S from Spansion) and it is correct.

2) Is Zynq Production Silicon?

yes,I checked it.This is part of the IMPACT report when it is connected to JTAG

Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc7z020, Version : 2

3) Is the JTAG chain operating properly?

yes it is correct.i can program fpga and run my helloworld project in SDK.and see its output in the Serial terminal.

4) In which phase of booting Zynq is failing? BootROM or FSBL?

 yes,I checked it.This is  the FSBL project debug report

in jtag boot mode debug report is

Devcfg driver initialized
Silicon Version 3.1
Boot mode is JTAG

in qspi boot mode debug report is

Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI

Single Flash Information
FlashID=0x1 0x20 0x18
SPANSION 128M Bits
QSPI is in single flash connection
QSPI is in 4-bit mode
QSPI Init Done
Flash Base Address: 0xFC000000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x000F6EC0
Data Word Len: 0x000F6EC0
Partition Word Len:0x000F6EC0
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000045D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD16B7E
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000F30

 

5) Are SDK and iMPACT failing to program?

no.qspi program successfully. this is the program report in sdk

 

 

 

****** Xilinx Program Flash
****** Program Flash v2018.2 (64-bit)
**** SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-DLC9LP-00000000000000
Device 0: jsn-DLC9LP-00000000000000-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA220 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA220
===== mrd->addr=0xF8000100, data=0x00028008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x00028008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001452C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001452C0
===== mrd->addr=0xF8000108, data=0x0001E008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0001E008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B

 


U-Boot 2018.01-00071-g0018654-dirty (May 01 2018 - 11:18:16 -0600)

 

Model: Zynq CSE QSPI Board

Board: Xilinx Zynq

Silicon: v3.1

DRAM: 256 KiB

WARNING: Caches not enabled

Using default environment

 

In: dcc

Out: dcc

Err: dcc

Zynq> sf probe 0 0 0


SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB

Zynq> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 400000


SF: 4194304 bytes @ 0x0 Erased: OK

Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 12 sec.
Performing Blank Check Operation...
0%...sf read FFFC0000 0 10000


device 0 offset 0x0, size 0x10000

SF: 65536 bytes @ 0x0 Read: OK

Zynq> cmp.b FFFC0000 FFFD0000 10000

.

.

.

.

Zynq> cmp.b FFFC0000 FFFD0000 10000


Total of 65536 byte(s) were the same

Zynq> 100%
sf read FFFC0000 3F0000 9248


device 0 offset 0x3f0000, size 0x9248

SF: 37448 bytes @ 0x3f0000 Read: OK

Zynq> cmp.b FFFC0000 FFFD0000 9248


Total of 37448 byte(s) were the same

Zynq> INFO: [Xicom 50-44] Elapsed time = 77 sec.
Verify Operation successful.

Flash Operation Successful

 

6) Is it working using u-boot?

i used vivado/sdk 2018.2 and xsct console donot support XMD.this was not a problem in an older version of the vivado

xsct% xmd
xsct% invalid command name "xmd"

7) Is the board design to support the QSPI frequency used for programming?

I considered qspi speed in design of qspi pcb track.but How i Use u-boot and double check the clock settings to verify the QSPI frequency in sdk?

8) Is the Xilinx standalone example working?

Yes, it works correctly

 

In addition to the above.I also tested this example(xqspips_g128_flash_example.c) from embeddedsw-master

embeddedsw-master\embeddedsw-master\XilinxProcessorIPLib\drivers\qspips\examples

And the output of this test on the serial port is as follows:

QSPI Greater than 128Mb Flash Example Test
FlashID=0x1 0x20 0x18

Successfully ran QSPI Greater than 128Mb Flash Ex Test

 

0 Kudos
Moderator
Moderator
26 Views
Registered: ‎03-19-2014

Re: qspi boot problem

Thanks for the information. It looks like your QSPI is functioning correctly. You said a boot.bin does not program the PL. Can you program the PL from SDK Xilinx -> Program FPGA command?

The FSBL debug output you showed ended at PCAP:StatusReg = 0x40000F30 -- is that where it ends? If not, can you provide the FSBL debug?

Are you seeing activity on INIT_B? (refer to UG470 )

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