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Observer
Observer
2,224 Views
Registered: ‎05-21-2008

2nd axi interconnect, reset added to IP when imported??????

  I created another axi_lite ip through the XPS wizard for Zynq, and imported it into the project.  I'm using the Zynq ZC7020 board.

 

  a reset_1 ip was added (proc_sys_reset), along with axi_interconnect_2 and axi2axi_connector_1.  An external RESET is required, and I don't know what to do with it. (Ext_reset_in ==> External Ports::RESET)

 

  Why?

 

  DRC now complains that there is a Dcm_locked missing in the MHS.   What????

 

  What should I do now?  I don't need Reset in my ip.  

 

    None of the Google or Xilinx forum searches covered this issue.

 

   As a test, I added an additional previously created IP to the project, and it doesn't do this, it just uses the current system without modification, so I'm confused.

 

 I have 16 ip's connected to the axi interconnect, so I can see the need for another interconnect with a bridge.  I just don't know how to fight the reset requirement. 

 

Please help, any suggestions accepted.  Because of corporate circumstances, I'm temporarily stuck (several months) with Plan Ahead, and can't move to Vivado.

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Xilinx Employee
Xilinx Employee
2,193 Views
Registered: ‎07-21-2014

Hi,

 

in vivado tcl console type:

report_ip_status

this will give you the table reporting all the IPs, their current status and steps that are to be performed if you have some error regarding IP. 

if you are unable to understand the info you can post that it so as to undestand the issue

 

thanks

shreyas

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Xilinx Employee
Xilinx Employee
2,177 Views
Registered: ‎10-24-2013

Hi,
Moving this post to Embedded Development Tools
Thanks,Vijay
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