03-24-2019 05:38 AM
Under 2018.3 I am developing a system that will fit entirely within the OCM of a Zynq 7010 or 7020 (TBD), and therefore want to eliminate DDR3 from the BOM to simplify the board and to not waste money on chips that won't be used at runtime.
SDK Bug 1:
While I can get the PL and PS up and running from QSPI when DDR is included, the FSBL generator isn't properly obeying the system configuration when DDR is absent - almost the whole bootloader is wrapped in a #ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR statement which causes it to fail if DDR is not present.
SDK Bug 2:
When trying to tell a generated FSBL to XIP, the .bif flag xip_mode is not settable in the Bootgen UI, and appears to be overwritten when manually set.
Some insight on when these bugs will be corrected would be very much appreciated.
03-25-2019 12:38 AM
1. Does your HDF file contain any DDR reference? I mean, if your Vivado design does not have DDR memory enabled then your HDF file will not have any reference to it and the xparameters.h file generated within the BSP should not have XPAR_PS7_DDR_0_S_AXI_BASEADDR defined.
2. If not wrong the GUI mode does not provide XIP mode capability so whenever you use the Bootgen GUI it saves your latest configuration (without XIP) overwritting the configuration. Right now the way to use XIP is manually calling to bootgen rather than using the GUI mode.
03-25-2019 09:41 AM - edited 03-25-2019 09:53 AM
1) DDR is not defined in the block diagram or the exported hardware. The PS application linker script respects this and places all sections in OCM, but the generated FSBL does not and still has references and checks on DDR. It's a clear bug in the FSBL.
2) The GUI limitation is unfortunate.
03-25-2019 12:39 PM
SDK Bug 1:
I'm not sure what do you mean with "which causes it fail", I mean, the FSBL does check if you system have DDR enabled (#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR) to perform the required steps. As you already said almost everything in the FSBL main function is within the conditional branch and actually if you don't have DDR enabled in Zynq-7000, FSBL is intended to print an error at runtime. This is because FSBL defautl code on Zynq-7000 is not ment to be used on DDRless system so manual changes are required.
SDK Bug 2:
The XIP feature never have been really popular so I guess that's why there was not too much request on implementing this Bootgen option within the GUI. I will report your feedback to development team so they can take into account for the future.
03-25-2019 12:47 PM
Rather than worrying too much about the minor XIP gui bug/feature request, I think it would be much more productive to offer an FSBL (since we *require* one to even flash the chip since 2017.1?) which works on DDRless Zynqs. Requiring DDR use adds ~40% to the cost of lower end Zynq parts.
03-27-2019 12:39 AM
The fact that FSBL is not provided as DDRless ready out of the box does not mean that cannot be used for these use cases, actually the AR#56044 is published since 2015 to document the steps required for such use case.
PD: For ZynqMPSoC devices the non DDRless support is out of the box.