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Registered: ‎03-22-2016

3-Wire SPI using Quad SPI IP with XSpi library in Microblaze

Hello,

I'm trying to use the Quad SPI IP to communicate with a 3-wire SPI device. From what I can tell, the Quad SPI IP doesn't support that functionality natively.

I see two hurdles I need to overcome to achieve this:

  1. I need to attach the MOSI and MISO pins of the QSPI to an IOBUF and control the tristate bit to switch between read and write.
  2. I need to switch that tristate bit at the appropriate time during a transfer. In my case, I need to transfer 2 bytes of address, switch the tri-state to read mode, then transfer 1 byte.

For #1, I discovered that it's possible to override the one-hot protection of the slave select to allow an extra slave select pin to be used as a read/write toggle. I could also use a GPIO, but it seemed cleaner to keep everything within the SPI block.

For #2, however, what I found is that there's no obvious way to do anything during a transfer without circumventing all of the driver code. I can instead issue a 2-byte transfer followed by a 1-byte transfer, which seemed like it should work, but the slave select is being deasserted between transfers. The external device I am connecting to resets the SPI transaction when the slave select is deasserted. I need to find some way to change the slave select (or a GPIO elsewhere) without it being "reset" to deasserted.

Has anyone tried to do something like this? If so, what did you use to control the tri-state, and how did you swap it mid-transfer?

EDIT: Sorry, I just realized this is the wrong forum, this should really be in Embedded Processor System Design.

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Registered: ‎04-13-2015

@jeffsimpson 

Have you looked into using the SPI module instead ? - it is the 3 wire I/F you are looking for. As for using the Quad SPI - that I/F module is tailored for NOR serial flash devices and only supports these flash device types of transfers.

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@ericv wrote:

@jeffsimpson 

Have you looked into using the SPI module instead ? - it is the 3 wire I/F you are looking for. As for using the Quad SPI - that I/F module is tailored for NOR serial flash devices and only supports these flash device types of transfers.


Can you link to the IP you're referring to? I don't see anything by that name in the IP catalog in Vivado 2018.3 for US/US+ parts. In fact, the one I'm using is the only result for "SPI" in the IP catalog.

https://www.xilinx.com/products/intellectual-property/axi_quadspi.html

The documentation for it says that it supports standard SPI as well as the dual/quad modes meant for flash devices.

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Registered: ‎04-13-2015

@jeffsimpson 

you're right, it's the same I was thnking :-)

As for how to control the CS yourself, did you try setting CS in manual mode i.e. over-riding the library set-up (SPICR bit #7) and controlling ourside the driver the SPI system enable (SPICR bit #1), which will then directly control CS?

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Registered: ‎03-22-2016


@ericv wrote:

@jeffsimpson 

you're right, it's the same I was thnking :-)

As for how to control the CS yourself, did you try setting CS in manual mode i.e. over-riding the library set-up (SPICR bit #7) and controlling ourside the driver the SPI system enable (SPICR bit #1), which will then directly control CS?


I did try setting CS in manual mode, but using the driver, still. I did consider a rewrite of the driver to do what I wanted, but it seemed overkill.

I was able things completely working by bypassing the provded CS/SS entirely and using a GPIO block to generate both the CS and a tri-state control bit for switching between MISO and MOSI. Having to use GPIO is a "hack", in my opinion, so I was hoping somebody out there had a better solution for how to use the Quad SPI IP in a 3-wire mode.

EDIT: Manual CS control while still using the driver didn't do what I was hoping it would. Instead of the IP controlling CS, the driver did. Really what I wanted was for the driver to also leave CS alone and let me do it in my own code. It looks like the only way to do that is to modify the driver or use an alternate signal for CS (a GPIO block). Neither is really what I'd call a "clean" option, unfortunately.

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Registered: ‎03-10-2020

Hello,

I want to configure an ADC via 3 wire SPI. I was thinking of applying first solution.

Did you find a proper solution for 3 wire AXI Quad SPI?

Best regards.

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@harun123 wrote:

Did you find a proper solution for 3 wire AXI Quad SPI?


I wouldn't call it "proper", but it did work. I used a GPIO block to control both the SS/CS lines and the tristate control lines. I issued read and write transactions separately using the Xilinx SPI driver library, unmodified. I just wrote a small amount of code specific to my application to make switching between slave devices and read/write modes easier/cleaner.

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