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yinlinlijuan
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Registered: ‎03-14-2012

A mistake with AXI_VDMA IPcore

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Hi, I want to write a frame to DDR2 through AXI_VDMA IPcore, but I have met a strange mistate.

 

My image data size is 1280*1024, all the data which was writen to DDR2 is right except for the first line of image.

 

This error is as follows :

 

In  axis_s2mm_tdata interface of axi_vdma, the data stream is 0x03020100, 0x07060504, 0x0B0A0908, 0x0F0E0D0C, 0x13121110, ... ,

 

But in axi_s2mm_wdata interface of axi_vdma, the data stream is 0x03020100, 0x07060504, 0x03020100, 0x07060504, 0x0B0A0908, 0x0F0E0D0C, 0x13121110,

 

That is to say, the data of the first line  repeated this two data : 0x03020100, 0x07060504. Why ?

 

Need your help, Thanks.

 

 

axi_s2mm_timing.jpg

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yinlinlijuan
Adventurer
Adventurer
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Registered: ‎03-14-2012

OK,

 

My ISE version is 14.2.

 

the registers of axi_vdma are set as follows :

 

always @(write_index)
begin
case (write_index)
// AXI VDMA 0 Set Up
1: m_axi_lite_awaddr <= 32'h7E220000; //AXI_VDMA_0 MM2S_DMACR
2: m_axi_lite_awaddr <= 32'h7E220004; //AXI_VDMA_0 MM2S_DMASR
3: m_axi_lite_awaddr <= 32'h7E220054; //AXI_VDMA_0 MM2S_HSIZE
4: m_axi_lite_awaddr <= 32'h7E220058; //AXI_VDMA_0 MM2S_DLYSTRIDE
5: m_axi_lite_awaddr <= 32'h7E22005C; //AXI_VDMA_0 MM2S_START_ADDR1
6: m_axi_lite_awaddr <= 32'h7E220060; //AXI_VDMA_0 MM2S_START_ADDR2
7: m_axi_lite_awaddr <= 32'h7E220064; //AXI_VDMA_0 MM2S_START_ADDR3
8: m_axi_lite_awaddr <= 32'h7E220030; //AXI_VDMA_0 S2MM_DMACR
9: m_axi_lite_awaddr <= 32'h7E220034; //AXI_VDMA_0 S2MM_DMASR
10: m_axi_lite_awaddr <= 32'h7E2200A4; //AXI_VDMA_0 S2MM_HSIZE
11: m_axi_lite_awaddr <= 32'h7E2200A8; //AXI_VDMA_0 S2MM_DLYSTRIDE
12: m_axi_lite_awaddr <= 32'h7E2200AC; //AXI_VDMA_0 S2MM_START_ADDR1
13: m_axi_lite_awaddr <= 32'h7E2200B0; //AXI_VDMA_0 S2MM_START_ADDR2
14: m_axi_lite_awaddr <= 32'h7E2200B4; //AXI_VDMA_0 S2MM_START_ADDR3
15: m_axi_lite_awaddr <= 32'h7E220050; //AXI_VDMA_0 MM2S_VSIZE
16: m_axi_lite_awaddr <= 32'h7E2200A0; //AXI_VDMA_0 S2MM_VSIZE
default: m_axi_lite_awaddr <= 32'h00000000;
endcase
end

always @(write_index)
begin
case (write_index)
// AXI VDMA 0 Set Up
1: m_axi_lite_wdata <= 32'h0001000B; //AXI_VDMA_0 MM2S_DMACR (Sets RS=1, Circular Buffer=1, Threshold=default)
2: m_axi_lite_wdata <= 32'h00007770; //AXI_VDMA_0 MM2S_DMASR (Clears any interrupt or error status)
3: m_axi_lite_wdata <= 32'h00000500; //AXI_VDMA_0 MM2S_HSIZE (
4: m_axi_lite_wdata <= 32'h01000500; //AXI_VDMA_0 MM2S_DLYSTRIDE (Delay = 0, Stride = 1400h)
5: m_axi_lite_wdata <= 32'hA7000000; //AXI_VDMA_0 MM2S_START_ADDR1
6: m_axi_lite_wdata <= 32'hA7400000; //AXI_VDMA_0 MM2S_START_ADDR2
7: m_axi_lite_wdata <= 32'hA7800000; //AXI_VDMA_0 MM2S_START_ADDR3
8: m_axi_lite_wdata <= 32'h00010003; //AXI_VDMA_0 S2MM_DMACR (Sets RS=1, Circular Buffer=1, Threshold=default)
9: m_axi_lite_wdata <= 32'h00007770; //AXI_VDMA_0 S2MM_DMASR (Clears any interrupt or error status)
10: m_axi_lite_wdata <= 32'h00000500; //AXI_VDMA_0 S2MM_HSIZE (
11: m_axi_lite_wdata <= 32'h00000500; //AXI_VDMA_0 S2MM_DLYSTRIDE (Delay = 1, Stride = 1400h)
12: m_axi_lite_wdata <= 32'hA7000000; //AXI_VDMA_0 S2MM_START_ADDR1
13: m_axi_lite_wdata <= 32'hA7400000; //AXI_VDMA_0 S2MM_START_ADDR2
14: m_axi_lite_wdata <= 32'hA7800000; //AXI_VDMA_0 S2MM_START_ADDR3
15: m_axi_lite_wdata <= 32'h000003C0; //AXI_VDMA_0 MM2S_VSIZE (Vertical Size = 720) - Starts mm2s
16: m_axi_lite_wdata <= 32'h000003C0; //AXI_VDMA_0 S2MM_VSIZE (Vertical Size = 720) - Starts s2mm
default: m_axi_lite_wdata <= 32'h00000000;
endcase
end

 

So, my image size is 1280*960,  there are three photograph of timing of chipscope in attachments.

 

Thanks.

 

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bwiec
Xilinx Employee
Xilinx Employee
4,360 Views
Registered: ‎08-02-2011
Can you provide some more info about your system? i.e. mhs, software, register space, etc.

Also, have you chipscoped the stream side to verify that the data is what you expect? Can you post that?

What are your hsize and stride settings?
www.xilinx.com
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yinlinlijuan
Adventurer
Adventurer
5,490 Views
Registered: ‎03-14-2012

OK,

 

My ISE version is 14.2.

 

the registers of axi_vdma are set as follows :

 

always @(write_index)
begin
case (write_index)
// AXI VDMA 0 Set Up
1: m_axi_lite_awaddr <= 32'h7E220000; //AXI_VDMA_0 MM2S_DMACR
2: m_axi_lite_awaddr <= 32'h7E220004; //AXI_VDMA_0 MM2S_DMASR
3: m_axi_lite_awaddr <= 32'h7E220054; //AXI_VDMA_0 MM2S_HSIZE
4: m_axi_lite_awaddr <= 32'h7E220058; //AXI_VDMA_0 MM2S_DLYSTRIDE
5: m_axi_lite_awaddr <= 32'h7E22005C; //AXI_VDMA_0 MM2S_START_ADDR1
6: m_axi_lite_awaddr <= 32'h7E220060; //AXI_VDMA_0 MM2S_START_ADDR2
7: m_axi_lite_awaddr <= 32'h7E220064; //AXI_VDMA_0 MM2S_START_ADDR3
8: m_axi_lite_awaddr <= 32'h7E220030; //AXI_VDMA_0 S2MM_DMACR
9: m_axi_lite_awaddr <= 32'h7E220034; //AXI_VDMA_0 S2MM_DMASR
10: m_axi_lite_awaddr <= 32'h7E2200A4; //AXI_VDMA_0 S2MM_HSIZE
11: m_axi_lite_awaddr <= 32'h7E2200A8; //AXI_VDMA_0 S2MM_DLYSTRIDE
12: m_axi_lite_awaddr <= 32'h7E2200AC; //AXI_VDMA_0 S2MM_START_ADDR1
13: m_axi_lite_awaddr <= 32'h7E2200B0; //AXI_VDMA_0 S2MM_START_ADDR2
14: m_axi_lite_awaddr <= 32'h7E2200B4; //AXI_VDMA_0 S2MM_START_ADDR3
15: m_axi_lite_awaddr <= 32'h7E220050; //AXI_VDMA_0 MM2S_VSIZE
16: m_axi_lite_awaddr <= 32'h7E2200A0; //AXI_VDMA_0 S2MM_VSIZE
default: m_axi_lite_awaddr <= 32'h00000000;
endcase
end

always @(write_index)
begin
case (write_index)
// AXI VDMA 0 Set Up
1: m_axi_lite_wdata <= 32'h0001000B; //AXI_VDMA_0 MM2S_DMACR (Sets RS=1, Circular Buffer=1, Threshold=default)
2: m_axi_lite_wdata <= 32'h00007770; //AXI_VDMA_0 MM2S_DMASR (Clears any interrupt or error status)
3: m_axi_lite_wdata <= 32'h00000500; //AXI_VDMA_0 MM2S_HSIZE (
4: m_axi_lite_wdata <= 32'h01000500; //AXI_VDMA_0 MM2S_DLYSTRIDE (Delay = 0, Stride = 1400h)
5: m_axi_lite_wdata <= 32'hA7000000; //AXI_VDMA_0 MM2S_START_ADDR1
6: m_axi_lite_wdata <= 32'hA7400000; //AXI_VDMA_0 MM2S_START_ADDR2
7: m_axi_lite_wdata <= 32'hA7800000; //AXI_VDMA_0 MM2S_START_ADDR3
8: m_axi_lite_wdata <= 32'h00010003; //AXI_VDMA_0 S2MM_DMACR (Sets RS=1, Circular Buffer=1, Threshold=default)
9: m_axi_lite_wdata <= 32'h00007770; //AXI_VDMA_0 S2MM_DMASR (Clears any interrupt or error status)
10: m_axi_lite_wdata <= 32'h00000500; //AXI_VDMA_0 S2MM_HSIZE (
11: m_axi_lite_wdata <= 32'h00000500; //AXI_VDMA_0 S2MM_DLYSTRIDE (Delay = 1, Stride = 1400h)
12: m_axi_lite_wdata <= 32'hA7000000; //AXI_VDMA_0 S2MM_START_ADDR1
13: m_axi_lite_wdata <= 32'hA7400000; //AXI_VDMA_0 S2MM_START_ADDR2
14: m_axi_lite_wdata <= 32'hA7800000; //AXI_VDMA_0 S2MM_START_ADDR3
15: m_axi_lite_wdata <= 32'h000003C0; //AXI_VDMA_0 MM2S_VSIZE (Vertical Size = 720) - Starts mm2s
16: m_axi_lite_wdata <= 32'h000003C0; //AXI_VDMA_0 S2MM_VSIZE (Vertical Size = 720) - Starts s2mm
default: m_axi_lite_wdata <= 32'h00000000;
endcase
end

 

So, my image size is 1280*960,  there are three photograph of timing of chipscope in attachments.

 

Thanks.

 

View solution in original post

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yinlinlijuan
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Registered: ‎03-14-2012

Addtionally, my system structure is like this.

 

I send image data stream in axis_s2mm interface of axi_vdma, and recive data stream in axis_mm2s of axi_vdma.

 

The axi_s2mm and axi_mm2s interface of axi_vdma is connected to axi_s6_ddr IPcore directly.

 

that is all my system.

 

Thanks.

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akanksha112
Adventurer
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Registered: ‎04-07-2011

Hi

 

If you are still active on this post , please revert. I have some problem with VDMA and would be glad if you could offer me some help on that.

 

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