Hi, everyone. I am a newbie and have a problem on PLB bus.
It seems quite simple, but I have got no idea.
I want to write a program in VHDL which is about a single master write and read data from DDR through PLB v4.6. As there is only one master, I think no arbitration is needed. But I do not know how to write the code, since there is only one master. The PLB v4.6 specifications are full of arbitration. Is it obligatory to use the arbitration?
I searched, but did not get any sample codes.
If anyone may point me in the direction or issue some reference, I would really appreciate it.