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Observer ssong94
Observer
1,329 Views
Registered: ‎03-19-2018

ACP port for Zynq board[BD 41-1629] </processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master

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Hi, I'm trying to use the ACP port instead of the HP port for Zynq board. But when I try to validate the design, the following error appeared: [BD 41-1629] </processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master spaces.The following is the block design.

 

Capture.JPG

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Moderator
Moderator
1,634 Views
Registered: ‎07-01-2015

Re: ACP port for Zynq board[BD 41-1629] </processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master

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Hi @ssong94,

 

Please check the address editor tab and see if the slave is mapped.

If not try auto assign address. 

Thanks,
Arpan
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3 Replies
Moderator
Moderator
1,635 Views
Registered: ‎07-01-2015

Re: ACP port for Zynq board[BD 41-1629] </processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master

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Hi @ssong94,

 

Please check the address editor tab and see if the slave is mapped.

If not try auto assign address. 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Newbie liu_osi
Newbie
1,152 Views
Registered: ‎04-24-2018

Re: ACP port for Zynq board[BD 41-1629] </processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master

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123.png

According to your method, I have encountered such a problem. Can you tell me how to solve it?

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Visitor pear
Visitor
930 Views
Registered: ‎05-23-2018

Re: ACP port for Zynq board[BD 41-1629] </processing_system7_0/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master

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You can choose "Include Segment", then the segment will be included and auto addressed. 

 

Thanks,

pear

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