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Explorer
Explorer
1,481 Views
Registered: ‎04-19-2016

AXI Chip2Chip between two Zynq chips

Hello,

 

*I try to send data from one Zynq chip to another Zynq's PS DDR3. But there is problem about the addressing and I have received VDMADecErr error from VDMA in Master side. I gave address [2000_0000 to 3FFF_FFFF] to VDMA for AXI Chip2Chip IP, due to the Slave side Zynq PS DDR3. Because addresses of Master and Slave side of an Axi Chip2Chip bus are the exactly the same. But infact at the same time this address falls into the Master side Zynq PS DDR3. Error is this ?  

 

*In this case, how can I send data to Slave side Zynq PS DDR3, by using VMDA in Master side through Axi Chip2Chip ? 

 

You can see whole basic flow below ; 

 

Thank you, 

 

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AxiC2C_System.JPG
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3 Replies
Xilinx Employee
Xilinx Employee
1,436 Views
Registered: ‎07-23-2012

Re: AXI Chip2Chip between two Zynq chips

The address range 0x10_0000 to 0x3fff_ffff is the DDR address space that can be accessed by all interconnect masters.

So, we can access this address range from AXI VDMA on chip1 and AXI C2C on chip2. Now, coming to your query on address overlap, I would recommend you to make the address non-overlapping as in AXI VDMA IP can access the address range from 0x10_0000 to 0x2FFF_FFFF (something like this) on chip1 and 0x3000_0000 to 0x3fff_ffff on chip2.
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Explorer
Explorer
1,397 Views
Registered: ‎04-19-2016

Re: AXI Chip2Chip between two Zynq chips

Dear @smarell,

 

We have just tried the option you said. But still received VDMADecErr. In fact it is trivial. Because, VDMA could not decode the address [2000_0000], due to the VDMA does not see [2000_0000] in Master side. However same VDMA see address [2000_0000] of Chip2's (slave) PS DDR3 over Axi Chip2Chip. 

 

I am afraid that we could not directly send data from Zynq chip1(master) to  Zynq chip2's (slave) PS DDR3 over Axi Chip2Chip. In fact it is seen from this XAPP1160 application note. There is only two cases in that application note ; one is MicroBlaze(Master)  - MicroBlaze (Slave) and other is MicroBlaze(Master) -  Zynq(Slave) . So there is no our case Zynq(Master) - Zynq(Slave).

 

Regards,

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Xilinx Employee
Xilinx Employee
1,355 Views
Registered: ‎02-26-2014

Re: AXI Chip2Chip between two Zynq chips

Hi,

 

As AXI system I is different from AXI system II, they can have overlapping addresses.

If you are getting Dec Error on VDMA, did you insert ILA and see the AXI transaction?

You need to see the source IP that is generating the decode error.

 

If the VDMA is directly conected to AXI chip to chip IP, without interconnect, you can suspect this IP itself. You can check the link status of the IP.

 

Regards,

Ravi

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