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phaser_phase
Visitor
Visitor
370 Views
Registered: ‎10-14-2019

AXI-Lite write fails on some data

 

Hi, I am currently working on a project with an Avnet PicoZed board.

I have several AXI-Lite Peripherals on my PL and a simple software on my Zynq that read and write data on the AXI from / to the PL.

One of the AXI-Lite IP is used to load some filter coefficients from the PS to the PL.My issue comes from the AXI-Lite that does not correctly write the data.

The mapping is as follow:

-- slv_reg0(0) not used
s22b_filter_coeff <= slv_reg0(22 downto 1);
s22b_cstart        <= slv_reg0(23); -- not used
s22_filter_write_en <= slv_reg0(24);

On the software side, I have a for loop that loads the coefficients. After some investigation, I realized that some data "corrupts" what is written with the Xil_Out32().

Some exemple:

axi_write(my_base_addr, 0, 0); // set write_en+data to 0
axi_write(my_base_addr, 0, 0x1000000) // write_en 1 data = 0

Sucessfully works,

Here is the code if I want my data set to anything:

axi_write(my_base_addr, 0, 0); // set write_en+data to 0
u32 data ;
u32 axi_data = 0x1000000+(data&0x3FFFFF);
axi_write(my_base_addr, 0, 0x1000000+axi_data // write_en 1 and data

I put this in a for loop for testing and debugging.

This code works for some values that are a power of 2 but does not for others...

I use an ILA to debug the situation. I set the trigger condition on the rising edge of s22_filter_write_en and just check the number of triggers.

If it can help some information on my axi-lite ip: 

AXi-Lite 4 as a Slave, 16 slv registers (C_S_AXI_DATA_WIDTH = 32; C_S_AXI_ADDR_WIDTH = 6).

XSDK: 2018.1, Vivado: 2018.1, code: VHDL.

I use others IP that are similar to this and I don't have this issue...

Let me know if you need anything else, any help would be great!

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1 Reply
dgisselq
Scholar
Scholar
361 Views
Registered: ‎05-21-2015

@phaser_phase,

From the information you've provided above, it would be very difficult to state what your problem is.  Is there any way that you can share your code?  I'd be glad to run a formal verification check, and see if you are missing anything obvious.

Also, you should be aware that the standard Xilinx AXI-lite demo IP has bugs in it.  This version does not, in case you need a better example to work from.

Dan

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