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Visitor
Visitor
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Registered: ‎02-14-2017

AXI Stream output from BRAM

I am developing a custom IP core that takes an AXI Stream input and writes that data to a (rather large) BRAM and then streams the data out of the BRAM to an AXI Stream output (the output order is different from the input order, so this is not a normal FIFO). I am trying to get the logic right for the AXI handshaking signals (tready and tvalid), but am having a little trouble wrapping my head around how to do it properly. In general the AXI handshake seems backwards to me, but it also seems to make streaming from a BRAM especially difficult. I would prefer to use the output registers in the BRAM for the sake of timing, but that adds a pipeline delay that I am not sure I can handle if tready ever goes low. Since this is already a big BRAM, I would prefer not to add an AXI Stream Data FIFO directly afterwards. I do not really expect tready to be toggling low, but I also do not want to rely on it staying high either.

 

Is there any way to create an AXI Stream from data in a BRAM and use the BRAM's output register? Out of curiosity, I expanded an AXI Stream Data FIFO in a synthesized design to look at the BRAM in it and it is not using the output register. That does not make me hopeful that there is a solution.

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Teacher
Teacher
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Registered: ‎03-31-2012

Re: AXI Stream output from BRAM

@berryjatsc 

>> I would prefer to use the output registers in the BRAM for the sake of timing, but that adds a pipeline delay that I am not sure I can handle if tready ever goes low.

 

I am not sure what you think the problem is here. The way axi is defined, you can set tvalid at the same time data arrives at the (bram output or any other) register you use as output. It's just a matter of coding the RTL properly to manage the timing.

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Visitor
Visitor
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Registered: ‎02-14-2017

Re: AXI Stream output from BRAM

I think AXI being somewhat backwards from the way I have done streaming in the past has me overly confused. I was hung up on the fact that I should be able to have tvalid go high and stay high that I did not consider bringing it low sometimes to deal with the pipeline delay. That should work for a tready low-to-high transition. I think a tready high-to-low transition still needs more consideration, though. I have been looking at the axis register slice core and it seems to do something similar to what I have in my head that I need to do. Since tready and tvalid control the advance of the BRAM address, but the data is in a pipeline, I need some registers to hold the values that are in the pipe when tready goes low. Either that or some way to rewind the address. Both options seem overly complicated.

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