07-15-2015 06:50 AM
Hello, I want to acces memory with AXI4 intrerface, but I ned to write and read data using AXI stream. I connected 2 AXIS FIFOs to AXI DataMover and then I have 2 AXI master interfaces: one read only, second write only. I need to connect them to one R/W AXI interface. First idea was to use AXI Interconnect but I can't make it work. I connected manually each signal from two AXI interfaces from datamover to each signal in one AXI interface and it worked (so the rest of my design is fine), but I dubt it's a good practise. My current efforts look like that.
11-06-2015 11:45 AM
I'm facing a similar situation and I'm curious to see how you fixed it. My idea to handle this would be to create a 2 AXI slave and 1 AXI master aximm interfaces in a "pass-through" component that just hooks the 5 buses together (3 from write, 2 from read). Then create an IP out of it to be used in the IPI flow.
12-09-2015 03:17 AM
1) Have you been able to use the interconect as showned in the block design?
I found out that I was also trying the same configuration, but haven't been able to test it because the Datamover Steam Data Width (Auto) is stuck at 32 even though I have a 512 bus connected to it.
2) I am also curious, Did you design the AXI_datamover_CS module on your own? or where can I get it, I also spent some time designing something there which I have not been able to even simulate because of the Datamover configuration problem.
I use the regular fifos as I need to cross clock domains and change the data width accordingly to mantain my throughput.
3) Does anybody know how to force the datamover to take the 512 data width?
Any feedback regarding my three questions is apreciated.
12-09-2015 12:21 PM
Have you tried validating the block design? It's the mechanism to propagate various parameters like data width.
12-10-2015 01:57 AM
I did tried the Validation, and even it could synthesize, just with the warning about the different width.
But thanks to your sugestion, I tried once more with no result. then I double clicked on the port at the data mover block and there it said:
NOTE: Slave interfaces may not define Metadata until Validation has been run
As I am connecting a normal fifo to this input, which is not master axi, then I created an AXI fifo, with the correct width, validate, erase and finally with the correct width connect my normal fifo in the place I had it before.
now I will move forward with simulation and debugging
12-10-2015 10:24 AM
I'd venture to guess that it's not recognizing the width automatically because you're not connecting your AXIS slave to an AXIS master. If you want that, the FIFO would have to move inside the cmd_sts component and have it connected to an AXIS master port. Then the validation would move its width down to the datamover.